SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Hsieh, Chin-Tang, Ho, Lung-Hua, Wang, Chen-Yu, Kuo, Chun-Ting, Cheng, Pai-Sheng, Chiang, Chih-Hao, Hsu, Wen-Cheng, Kuo, Chih-Ming, Hu, Yu-Hui, Lin, Kung-An
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Hsieh, Chin-Tang
Ho, Lung-Hua
Wang, Chen-Yu
Kuo, Chun-Ting
Cheng, Pai-Sheng
Chiang, Chih-Hao
Hsu, Wen-Cheng
Kuo, Chih-Ming
Hu, Yu-Hui
Lin, Kung-An
description A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024194646A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024194646A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024194646A13</originalsourceid><addsrcrecordid>eNrjZBANdvX1dPb3cwl1DvEPUghwdPZ2dHflYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkYmhpYmZiZmjobGxKkCABomH-c</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR PACKAGE</title><source>esp@cenet</source><creator>Hsieh, Chin-Tang ; Ho, Lung-Hua ; Wang, Chen-Yu ; Kuo, Chun-Ting ; Cheng, Pai-Sheng ; Chiang, Chih-Hao ; Hsu, Wen-Cheng ; Kuo, Chih-Ming ; Hu, Yu-Hui ; Lin, Kung-An</creator><creatorcontrib>Hsieh, Chin-Tang ; Ho, Lung-Hua ; Wang, Chen-Yu ; Kuo, Chun-Ting ; Cheng, Pai-Sheng ; Chiang, Chih-Hao ; Hsu, Wen-Cheng ; Kuo, Chih-Ming ; Hu, Yu-Hui ; Lin, Kung-An</creatorcontrib><description>A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240613&amp;DB=EPODOC&amp;CC=US&amp;NR=2024194646A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240613&amp;DB=EPODOC&amp;CC=US&amp;NR=2024194646A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hsieh, Chin-Tang</creatorcontrib><creatorcontrib>Ho, Lung-Hua</creatorcontrib><creatorcontrib>Wang, Chen-Yu</creatorcontrib><creatorcontrib>Kuo, Chun-Ting</creatorcontrib><creatorcontrib>Cheng, Pai-Sheng</creatorcontrib><creatorcontrib>Chiang, Chih-Hao</creatorcontrib><creatorcontrib>Hsu, Wen-Cheng</creatorcontrib><creatorcontrib>Kuo, Chih-Ming</creatorcontrib><creatorcontrib>Hu, Yu-Hui</creatorcontrib><creatorcontrib>Lin, Kung-An</creatorcontrib><title>SEMICONDUCTOR PACKAGE</title><description>A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBANdvX1dPb3cwl1DvEPUghwdPZ2dHflYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkYmhpYmZiZmjobGxKkCABomH-c</recordid><startdate>20240613</startdate><enddate>20240613</enddate><creator>Hsieh, Chin-Tang</creator><creator>Ho, Lung-Hua</creator><creator>Wang, Chen-Yu</creator><creator>Kuo, Chun-Ting</creator><creator>Cheng, Pai-Sheng</creator><creator>Chiang, Chih-Hao</creator><creator>Hsu, Wen-Cheng</creator><creator>Kuo, Chih-Ming</creator><creator>Hu, Yu-Hui</creator><creator>Lin, Kung-An</creator><scope>EVB</scope></search><sort><creationdate>20240613</creationdate><title>SEMICONDUCTOR PACKAGE</title><author>Hsieh, Chin-Tang ; Ho, Lung-Hua ; Wang, Chen-Yu ; Kuo, Chun-Ting ; Cheng, Pai-Sheng ; Chiang, Chih-Hao ; Hsu, Wen-Cheng ; Kuo, Chih-Ming ; Hu, Yu-Hui ; Lin, Kung-An</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024194646A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Hsieh, Chin-Tang</creatorcontrib><creatorcontrib>Ho, Lung-Hua</creatorcontrib><creatorcontrib>Wang, Chen-Yu</creatorcontrib><creatorcontrib>Kuo, Chun-Ting</creatorcontrib><creatorcontrib>Cheng, Pai-Sheng</creatorcontrib><creatorcontrib>Chiang, Chih-Hao</creatorcontrib><creatorcontrib>Hsu, Wen-Cheng</creatorcontrib><creatorcontrib>Kuo, Chih-Ming</creatorcontrib><creatorcontrib>Hu, Yu-Hui</creatorcontrib><creatorcontrib>Lin, Kung-An</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hsieh, Chin-Tang</au><au>Ho, Lung-Hua</au><au>Wang, Chen-Yu</au><au>Kuo, Chun-Ting</au><au>Cheng, Pai-Sheng</au><au>Chiang, Chih-Hao</au><au>Hsu, Wen-Cheng</au><au>Kuo, Chih-Ming</au><au>Hu, Yu-Hui</au><au>Lin, Kung-An</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE</title><date>2024-06-13</date><risdate>2024</risdate><abstract>A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2024194646A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR PACKAGE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-11T23%3A01%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Hsieh,%20Chin-Tang&rft.date=2024-06-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024194646A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true