SEMICONDUCTOR PACKAGE

SEMICONDUCTOR PACKAGE

A semiconductor package includes a lower chip. A chip stacked structure is arranged on the lower chip. The chip stacked structure includes a plurality of upper chips. An underfill layer is disposed between the lower chip and the chip stacked structure and between the plurality of upper chips. A mold...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CHOI, Iljoo, HA, Sungmock, BAE, Jinsoo, NOH, Hyunggyun, BAE, Gunhee
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A semiconductor package includes a lower chip. A chip stacked structure is arranged on the lower chip. The chip stacked structure includes a plurality of upper chips. An underfill layer is disposed between the lower chip and the chip stacked structure and between the plurality of upper chips. A molding layer surrounds the underfill layer and the chip stacked structure. The lower chip has at least one lower trench positioned on an upper surface of the lower chip. At least one of the plurality of upper chips has at least one upper trench on an upper surface of the at least one of the plurality of upper chips.