MEMORY DEVICE AND OPERATING METHOD THEREOF

MEMORY DEVICE AND OPERATING METHOD THEREOF

A memory device includes a word line area that is between a bit line and a common source line. The word line area includes a plurality of stacks. A first area includes first stacks with a first resistance value in the word line area, a second area includes second stacks with a second resistance valu...

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Hauptverfasser: Choi, Yonghyuk, Yu, Jaeduk, Lee, Yohan
Format: Patent
Sprache:eng
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INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator Choi, Yonghyuk
Yu, Jaeduk
Lee, Yohan
description A memory device includes a word line area that is between a bit line and a common source line. The word line area includes a plurality of stacks. A first area includes first stacks with a first resistance value in the word line area, a second area includes second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value, a third area includes third stacks with a third resistance value that different from the first resistance value, and a processor is configured to control a recovery sequence of the first area, the second area, and the third area.
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PHYSICS
STATIC STORES
title MEMORY DEVICE AND OPERATING METHOD THEREOF
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