CIRCUIT DEVICE WITH MULTIPLE PARALLEL DATA PATHS
An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a...
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| creator | KARGUTH, Brian Jason VISALLI, Samuel Paul FUOCO, Charles Lance DENIO, Michael Anthony |
| description | An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024193112A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024193112A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024193112A13</originalsourceid><addsrcrecordid>eNrjZDBw9gxyDvUMUXBxDfN0dlUI9wzxUPAN9QnxDPBxVQhwDHL08XH1UXBxDHEE8kI8gnkYWNMSc4pTeaE0N4Oym2uIs4duakF-fGpxQWJyal5qSXxosJGBkYmhpbGhoZGjoTFxqgC7gycP</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CIRCUIT DEVICE WITH MULTIPLE PARALLEL DATA PATHS</title><source>esp@cenet</source><creator>KARGUTH, Brian Jason ; VISALLI, Samuel Paul ; FUOCO, Charles Lance ; DENIO, Michael Anthony</creator><creatorcontrib>KARGUTH, Brian Jason ; VISALLI, Samuel Paul ; FUOCO, Charles Lance ; DENIO, Michael Anthony</creatorcontrib><description>An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240613&DB=EPODOC&CC=US&NR=2024193112A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240613&DB=EPODOC&CC=US&NR=2024193112A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KARGUTH, Brian Jason</creatorcontrib><creatorcontrib>VISALLI, Samuel Paul</creatorcontrib><creatorcontrib>FUOCO, Charles Lance</creatorcontrib><creatorcontrib>DENIO, Michael Anthony</creatorcontrib><title>CIRCUIT DEVICE WITH MULTIPLE PARALLEL DATA PATHS</title><description>An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDBw9gxyDvUMUXBxDfN0dlUI9wzxUPAN9QnxDPBxVQhwDHL08XH1UXBxDHEE8kI8gnkYWNMSc4pTeaE0N4Oym2uIs4duakF-fGpxQWJyal5qSXxosJGBkYmhpbGhoZGjoTFxqgC7gycP</recordid><startdate>20240613</startdate><enddate>20240613</enddate><creator>KARGUTH, Brian Jason</creator><creator>VISALLI, Samuel Paul</creator><creator>FUOCO, Charles Lance</creator><creator>DENIO, Michael Anthony</creator><scope>EVB</scope></search><sort><creationdate>20240613</creationdate><title>CIRCUIT DEVICE WITH MULTIPLE PARALLEL DATA PATHS</title><author>KARGUTH, Brian Jason ; VISALLI, Samuel Paul ; FUOCO, Charles Lance ; DENIO, Michael Anthony</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024193112A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>KARGUTH, Brian Jason</creatorcontrib><creatorcontrib>VISALLI, Samuel Paul</creatorcontrib><creatorcontrib>FUOCO, Charles Lance</creatorcontrib><creatorcontrib>DENIO, Michael Anthony</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KARGUTH, Brian Jason</au><au>VISALLI, Samuel Paul</au><au>FUOCO, Charles Lance</au><au>DENIO, Michael Anthony</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CIRCUIT DEVICE WITH MULTIPLE PARALLEL DATA PATHS</title><date>2024-06-13</date><risdate>2024</risdate><abstract>An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | CIRCUIT DEVICE WITH MULTIPLE PARALLEL DATA PATHS |
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