ADVANCED INTERCONNECTION FOR WAFER ON WAFER PACKAGING

A semiconductor device assembly including a first module having one or more memory arrays, each of the one or more memory arrays being connected to a plurality of landing pads of the first module; and a second module having complementary metal-oxide-semiconductor devices, the second module including a plurality of socket shallow trench isolation (STI) regions disposed in a substrate of the second module, a plurality of metal routing layers connected to corresponding CMOS devices, a plurality of a first type of via contacts each being connected to a corresponding one of the plurality of metal routing layers, and a plurality of a second type of via contacts each being connected to a corresponding one of the plurality of landing pads of the first module, wherein the plurality of the first type of via contacts and the plurality of the second via contacts pass through the plurality of socket STI regions.