DIELECTRIC PROTECTION LAYER IN MIDDLE-OF-LINE INTERCONNECT STRUCTURE MANUFACTURING METHOD

In some embodiments, the present disclosure relates to an integrated chip including a gate electrode over a substrate. A pair of source/drain regions are disposed in the substrate on opposing sides of the gate electrode. A dielectric layer is over the substrate. An etch stop layer is between the gat...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Liu, Hao-Heng, Huang, Kuan-Da, Lin, Li-Te
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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