NAMED AND CLUSTER BARRIERS

NAMED AND CLUSTER BARRIERS

Embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. One embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. The graphics core inclu...

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Hauptverfasser: Fu, Fangwen, Mei, Chunhui, Wiegert, John A, Ashbaugh, Ben J, Liu, Yongsheng
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator Fu, Fangwen
Mei, Chunhui
Wiegert, John A
Ashbaugh, Ben J
Liu, Yongsheng
description Embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. One embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. The graphics core includes execution resources to execute an instruction via a plurality of hardware threads and barrier circuitry to synchronize execution of the plurality of hardware threads, wherein the barrier circuitry is configured to provide a plurality of re-usable named barriers.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title NAMED AND CLUSTER BARRIERS
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