SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of...
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| creator | Seo, Sunkyoung Kim, Hyoeun Kim, Dohyun |
| description | A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of first bonding pads and a first test pad that are on the second wiring layer. The second semiconductor chip includes a second wiring layer on a second substrate and a second passivation layer on the second wiring layer and that exposes at least portions of third bonding pads and second test pad that are provided on the second wiring layer. The first bonding pads and respective ones of the third bonding pads are directly bonded to each other. The first passivation layer and the second passivation layer are directly bonded to each other. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024128236A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024128236A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024128236A13</originalsourceid><addsrcrecordid>eNrjZPAOdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB1DfHwd1Hwd1PwdfQLdXN0DgkN8vRzVwjxcFXAqouHgTUtMac4lRdKczMou7mGOHvophbkx6cWFyQmp-allsSHBhsZGJkYGlkYGZs5GhoTpwoAQ5gulg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE</title><source>esp@cenet</source><creator>Seo, Sunkyoung ; Kim, Hyoeun ; Kim, Dohyun</creator><creatorcontrib>Seo, Sunkyoung ; Kim, Hyoeun ; Kim, Dohyun</creatorcontrib><description>A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of first bonding pads and a first test pad that are on the second wiring layer. The second semiconductor chip includes a second wiring layer on a second substrate and a second passivation layer on the second wiring layer and that exposes at least portions of third bonding pads and second test pad that are provided on the second wiring layer. The first bonding pads and respective ones of the third bonding pads are directly bonded to each other. The first passivation layer and the second passivation layer are directly bonded to each other.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240418&DB=EPODOC&CC=US&NR=2024128236A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240418&DB=EPODOC&CC=US&NR=2024128236A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Seo, Sunkyoung</creatorcontrib><creatorcontrib>Kim, Hyoeun</creatorcontrib><creatorcontrib>Kim, Dohyun</creatorcontrib><title>SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE</title><description>A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of first bonding pads and a first test pad that are on the second wiring layer. The second semiconductor chip includes a second wiring layer on a second substrate and a second passivation layer on the second wiring layer and that exposes at least portions of third bonding pads and second test pad that are provided on the second wiring layer. The first bonding pads and respective ones of the third bonding pads are directly bonded to each other. The first passivation layer and the second passivation layer are directly bonded to each other.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAOdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB1DfHwd1Hwd1PwdfQLdXN0DgkN8vRzVwjxcFXAqouHgTUtMac4lRdKczMou7mGOHvophbkx6cWFyQmp-allsSHBhsZGJkYGlkYGZs5GhoTpwoAQ5gulg</recordid><startdate>20240418</startdate><enddate>20240418</enddate><creator>Seo, Sunkyoung</creator><creator>Kim, Hyoeun</creator><creator>Kim, Dohyun</creator><scope>EVB</scope></search><sort><creationdate>20240418</creationdate><title>SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE</title><author>Seo, Sunkyoung ; Kim, Hyoeun ; Kim, Dohyun</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024128236A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Seo, Sunkyoung</creatorcontrib><creatorcontrib>Kim, Hyoeun</creatorcontrib><creatorcontrib>Kim, Dohyun</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Seo, Sunkyoung</au><au>Kim, Hyoeun</au><au>Kim, Dohyun</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE</title><date>2024-04-18</date><risdate>2024</risdate><abstract>A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of first bonding pads and a first test pad that are on the second wiring layer. The second semiconductor chip includes a second wiring layer on a second substrate and a second passivation layer on the second wiring layer and that exposes at least portions of third bonding pads and second test pad that are provided on the second wiring layer. The first bonding pads and respective ones of the third bonding pads are directly bonded to each other. The first passivation layer and the second passivation layer are directly bonded to each other.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T20%3A02%3A08IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Seo,%20Sunkyoung&rft.date=2024-04-18&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024128236A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |