SEMICONDUCTOR PACKAGE
A semiconductor package includes; a semiconductor substrate including a device region and an edge region, a first redistribution layer on a lower surface of the semiconductor substrate, a second redistribution layer on an upper surface of the semiconductor substrate, through vias vertically penetrat...
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creator | AHN, SEOK GEUN |
description | A semiconductor package includes; a semiconductor substrate including a device region and an edge region, a first redistribution layer on a lower surface of the semiconductor substrate, a second redistribution layer on an upper surface of the semiconductor substrate, through vias vertically penetrating the semiconductor substrate in the edge region to electrically connect the first redistribution layer and the second redistribution layer, and a circuit layer between the lower surface of the semiconductor substrate and the first redistribution layer. The circuit layer may include; a circuit element on the lower surface of the semiconductor substrate, a circuit wiring pattern electrically connected to the circuit element and the first redistribution layer, and a device interlayer dielectric layer substantially encompassing the circuit element and the circuit wiring pattern, wherein the circuit element and the circuit wiring pattern are disposed in the device region and not in the edge region. |
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The circuit layer may include; a circuit element on the lower surface of the semiconductor substrate, a circuit wiring pattern electrically connected to the circuit element and the first redistribution layer, and a device interlayer dielectric layer substantially encompassing the circuit element and the circuit wiring pattern, wherein the circuit element and the circuit wiring pattern are disposed in the device region and not in the edge region.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240418&DB=EPODOC&CC=US&NR=2024128176A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240418&DB=EPODOC&CC=US&NR=2024128176A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AHN, SEOK GEUN</creatorcontrib><title>SEMICONDUCTOR PACKAGE</title><description>A semiconductor package includes; a semiconductor substrate including a device region and an edge region, a first redistribution layer on a lower surface of the semiconductor substrate, a second redistribution layer on an upper surface of the semiconductor substrate, through vias vertically penetrating the semiconductor substrate in the edge region to electrically connect the first redistribution layer and the second redistribution layer, and a circuit layer between the lower surface of the semiconductor substrate and the first redistribution layer. The circuit layer may include; a circuit element on the lower surface of the semiconductor substrate, a circuit wiring pattern electrically connected to the circuit element and the first redistribution layer, and a device interlayer dielectric layer substantially encompassing the circuit element and the circuit wiring pattern, wherein the circuit element and the circuit wiring pattern are disposed in the device region and not in the edge region.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBANdvX1dPb3cwl1DvEPUghwdPZ2dHflYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkYmhkYWhuZmjobGxKkCABkSH90</recordid><startdate>20240418</startdate><enddate>20240418</enddate><creator>AHN, SEOK GEUN</creator><scope>EVB</scope></search><sort><creationdate>20240418</creationdate><title>SEMICONDUCTOR PACKAGE</title><author>AHN, SEOK GEUN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024128176A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>AHN, SEOK GEUN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AHN, SEOK GEUN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE</title><date>2024-04-18</date><risdate>2024</risdate><abstract>A semiconductor package includes; a semiconductor substrate including a device region and an edge region, a first redistribution layer on a lower surface of the semiconductor substrate, a second redistribution layer on an upper surface of the semiconductor substrate, through vias vertically penetrating the semiconductor substrate in the edge region to electrically connect the first redistribution layer and the second redistribution layer, and a circuit layer between the lower surface of the semiconductor substrate and the first redistribution layer. The circuit layer may include; a circuit element on the lower surface of the semiconductor substrate, a circuit wiring pattern electrically connected to the circuit element and the first redistribution layer, and a device interlayer dielectric layer substantially encompassing the circuit element and the circuit wiring pattern, wherein the circuit element and the circuit wiring pattern are disposed in the device region and not in the edge region.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR PACKAGE |
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