SIGNAL INTERFERENCE TESTING USING RELIABLE READ WRITE INTERFACE

A memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit. The test circuit generates a respective testing sequence of r...

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Hauptverfasser:	Askar, Tahsin, Magro, James R, Balakrishnan, Kedarnath, Brandl, Kevin M, Davanam, Naveen
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
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creator	Askar, Tahsin Magro, James R Balakrishnan, Kedarnath Brandl, Kevin M Davanam, Naveen
description	A memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit. The test circuit generates a respective testing sequence of read commands and write commands for each of the first channel and second channel, and causes the testing sequences to be transmitted over the first and second channels at least partially overlapping in time without selection by the first or second arbiters.
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subjects	INFORMATION STORAGE PHYSICS STATIC STORES
title	SIGNAL INTERFERENCE TESTING USING RELIABLE READ WRITE INTERFACE
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