NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION

A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis betwe...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Lie, Fee Li, Bergendahl, Marc A, Teehan, Sean, Cheng, Kangguo, Sporre, John R, Miller, Eric R
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Lie, Fee Li
Bergendahl, Marc A
Teehan, Sean
Cheng, Kangguo
Sporre, John R
Miller, Eric R
description A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024088268A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024088268A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024088268A13</originalsourceid><addsrcrecordid>eNrjZND3c_TzD_ZwdQ1RcPZw9PNz9dEN8dcN9g8NcnZVcPRzUXAJcvT0U_AM9vdxDPH09-NhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRiYGFhZGZhaOhsbEqQIAnjEm-Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION</title><source>esp@cenet</source><creator>Lie, Fee Li ; Bergendahl, Marc A ; Teehan, Sean ; Cheng, Kangguo ; Sporre, John R ; Miller, Eric R</creator><creatorcontrib>Lie, Fee Li ; Bergendahl, Marc A ; Teehan, Sean ; Cheng, Kangguo ; Sporre, John R ; Miller, Eric R</creatorcontrib><description>A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240314&amp;DB=EPODOC&amp;CC=US&amp;NR=2024088268A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240314&amp;DB=EPODOC&amp;CC=US&amp;NR=2024088268A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lie, Fee Li</creatorcontrib><creatorcontrib>Bergendahl, Marc A</creatorcontrib><creatorcontrib>Teehan, Sean</creatorcontrib><creatorcontrib>Cheng, Kangguo</creatorcontrib><creatorcontrib>Sporre, John R</creatorcontrib><creatorcontrib>Miller, Eric R</creatorcontrib><title>NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION</title><description>A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND3c_TzD_ZwdQ1RcPZw9PNz9dEN8dcN9g8NcnZVcPRzUXAJcvT0U_AM9vdxDPH09-NhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRiYGFhZGZhaOhsbEqQIAnjEm-Q</recordid><startdate>20240314</startdate><enddate>20240314</enddate><creator>Lie, Fee Li</creator><creator>Bergendahl, Marc A</creator><creator>Teehan, Sean</creator><creator>Cheng, Kangguo</creator><creator>Sporre, John R</creator><creator>Miller, Eric R</creator><scope>EVB</scope></search><sort><creationdate>20240314</creationdate><title>NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION</title><author>Lie, Fee Li ; Bergendahl, Marc A ; Teehan, Sean ; Cheng, Kangguo ; Sporre, John R ; Miller, Eric R</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024088268A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lie, Fee Li</creatorcontrib><creatorcontrib>Bergendahl, Marc A</creatorcontrib><creatorcontrib>Teehan, Sean</creatorcontrib><creatorcontrib>Cheng, Kangguo</creatorcontrib><creatorcontrib>Sporre, John R</creatorcontrib><creatorcontrib>Miller, Eric R</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lie, Fee Li</au><au>Bergendahl, Marc A</au><au>Teehan, Sean</au><au>Cheng, Kangguo</au><au>Sporre, John R</au><au>Miller, Eric R</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION</title><date>2024-03-14</date><risdate>2024</risdate><abstract>A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2024088268A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T06%3A56%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Lie,%20Fee%20Li&rft.date=2024-03-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024088268A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true