SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL a...
Gespeichert in:
Hauptverfasser: | , , , , , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | CHEN, SHUO-MAO JENG, SHIN-PUU LU, HSIANG-TAI HSU, FENGNG HONG, CHENG-YI LIN, CHEN-HUA LIN, CHIH-HSIEN CHEN, DAI-JANG WANG, MILL-JER YANG, CHAO-HSIANG |
description | A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024088124A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024088124A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024088124A13</originalsourceid><addsrcrecordid>eNrjZLAIdvX1dPb3cwl1DvEPUggOCQIyQoNcFRz9XBR8Hf1C3RxBfE8_dwVf1xAPfxeFEA_XIFd_Nx4G1rTEnOJUXijNzaDs5hri7KGbWpAfn1pckJicmpdaEh8abGRgZGJgYWFoZOJoaEycKgBAICnW</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF</title><source>esp@cenet</source><creator>CHEN, SHUO-MAO ; JENG, SHIN-PUU ; LU, HSIANG-TAI ; HSU, FENGNG ; HONG, CHENG-YI ; LIN, CHEN-HUA ; LIN, CHIH-HSIEN ; CHEN, DAI-JANG ; WANG, MILL-JER ; YANG, CHAO-HSIANG</creator><creatorcontrib>CHEN, SHUO-MAO ; JENG, SHIN-PUU ; LU, HSIANG-TAI ; HSU, FENGNG ; HONG, CHENG-YI ; LIN, CHEN-HUA ; LIN, CHIH-HSIEN ; CHEN, DAI-JANG ; WANG, MILL-JER ; YANG, CHAO-HSIANG</creatorcontrib><description>A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240314&DB=EPODOC&CC=US&NR=2024088124A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240314&DB=EPODOC&CC=US&NR=2024088124A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHEN, SHUO-MAO</creatorcontrib><creatorcontrib>JENG, SHIN-PUU</creatorcontrib><creatorcontrib>LU, HSIANG-TAI</creatorcontrib><creatorcontrib>HSU, FENGNG</creatorcontrib><creatorcontrib>HONG, CHENG-YI</creatorcontrib><creatorcontrib>LIN, CHEN-HUA</creatorcontrib><creatorcontrib>LIN, CHIH-HSIEN</creatorcontrib><creatorcontrib>CHEN, DAI-JANG</creatorcontrib><creatorcontrib>WANG, MILL-JER</creatorcontrib><creatorcontrib>YANG, CHAO-HSIANG</creatorcontrib><title>SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF</title><description>A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAIdvX1dPb3cwl1DvEPUggOCQIyQoNcFRz9XBR8Hf1C3RxBfE8_dwVf1xAPfxeFEA_XIFd_Nx4G1rTEnOJUXijNzaDs5hri7KGbWpAfn1pckJicmpdaEh8abGRgZGJgYWFoZOJoaEycKgBAICnW</recordid><startdate>20240314</startdate><enddate>20240314</enddate><creator>CHEN, SHUO-MAO</creator><creator>JENG, SHIN-PUU</creator><creator>LU, HSIANG-TAI</creator><creator>HSU, FENGNG</creator><creator>HONG, CHENG-YI</creator><creator>LIN, CHEN-HUA</creator><creator>LIN, CHIH-HSIEN</creator><creator>CHEN, DAI-JANG</creator><creator>WANG, MILL-JER</creator><creator>YANG, CHAO-HSIANG</creator><scope>EVB</scope></search><sort><creationdate>20240314</creationdate><title>SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF</title><author>CHEN, SHUO-MAO ; JENG, SHIN-PUU ; LU, HSIANG-TAI ; HSU, FENGNG ; HONG, CHENG-YI ; LIN, CHEN-HUA ; LIN, CHIH-HSIEN ; CHEN, DAI-JANG ; WANG, MILL-JER ; YANG, CHAO-HSIANG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024088124A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHEN, SHUO-MAO</creatorcontrib><creatorcontrib>JENG, SHIN-PUU</creatorcontrib><creatorcontrib>LU, HSIANG-TAI</creatorcontrib><creatorcontrib>HSU, FENGNG</creatorcontrib><creatorcontrib>HONG, CHENG-YI</creatorcontrib><creatorcontrib>LIN, CHEN-HUA</creatorcontrib><creatorcontrib>LIN, CHIH-HSIEN</creatorcontrib><creatorcontrib>CHEN, DAI-JANG</creatorcontrib><creatorcontrib>WANG, MILL-JER</creatorcontrib><creatorcontrib>YANG, CHAO-HSIANG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHEN, SHUO-MAO</au><au>JENG, SHIN-PUU</au><au>LU, HSIANG-TAI</au><au>HSU, FENGNG</au><au>HONG, CHENG-YI</au><au>LIN, CHEN-HUA</au><au>LIN, CHIH-HSIEN</au><au>CHEN, DAI-JANG</au><au>WANG, MILL-JER</au><au>YANG, CHAO-HSIANG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF</title><date>2024-03-14</date><risdate>2024</risdate><abstract>A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2024088124A1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-19T03%3A08%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHEN,%20SHUO-MAO&rft.date=2024-03-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024088124A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |