POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
A power semiconductor package includes: a die carrier having first and second opposite sides; and first and second power semiconductor dies each having first and second power electrodes on opposite sides. The second power electrodes face and are electrically coupled to the first side of the carrier....
Gespeichert in:
| Hauptverfasser: | , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Tommy Khoo, Chwee Pang Unterhofer, Katrin Schiele, Christian Uredat, Patrick Otremba, Ralf Gan, Thai Kee Lee, Teck Sim |
| description | A power semiconductor package includes: a die carrier having first and second opposite sides; and first and second power semiconductor dies each having first and second power electrodes on opposite sides. The second power electrodes face and are electrically coupled to the first side of the carrier. A molded body at least partially encapsulates the dies and has a first and second opposite sides and lateral sides connecting the first and second sides. First and second power contacts and first and second control contacts are arranged laterally next to each other. The first power electrode of the first die is electrically coupled to the first power contact by a first electrical connector. The first power electrode of the second die is electrically coupled to the second power contact by a second electrical connector. A width of each power contact is at least four times the width of each control contact. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024087995A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024087995A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024087995A13</originalsourceid><addsrcrecordid>eNrjZLAP8A93DVIIdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB1DfHwd1FwAwq7OToFeTo7hnj6uSuEeLgqBDv6uvIwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvjQYCMDIxMDC3NLS1NHQ2PiVAEAFv0rKg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME</title><source>esp@cenet</source><creator>Tommy Khoo, Chwee Pang ; Unterhofer, Katrin ; Schiele, Christian ; Uredat, Patrick ; Otremba, Ralf ; Gan, Thai Kee ; Lee, Teck Sim</creator><creatorcontrib>Tommy Khoo, Chwee Pang ; Unterhofer, Katrin ; Schiele, Christian ; Uredat, Patrick ; Otremba, Ralf ; Gan, Thai Kee ; Lee, Teck Sim</creatorcontrib><description>A power semiconductor package includes: a die carrier having first and second opposite sides; and first and second power semiconductor dies each having first and second power electrodes on opposite sides. The second power electrodes face and are electrically coupled to the first side of the carrier. A molded body at least partially encapsulates the dies and has a first and second opposite sides and lateral sides connecting the first and second sides. First and second power contacts and first and second control contacts are arranged laterally next to each other. The first power electrode of the first die is electrically coupled to the first power contact by a first electrical connector. The first power electrode of the second die is electrically coupled to the second power contact by a second electrical connector. A width of each power contact is at least four times the width of each control contact.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240314&DB=EPODOC&CC=US&NR=2024087995A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240314&DB=EPODOC&CC=US&NR=2024087995A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Tommy Khoo, Chwee Pang</creatorcontrib><creatorcontrib>Unterhofer, Katrin</creatorcontrib><creatorcontrib>Schiele, Christian</creatorcontrib><creatorcontrib>Uredat, Patrick</creatorcontrib><creatorcontrib>Otremba, Ralf</creatorcontrib><creatorcontrib>Gan, Thai Kee</creatorcontrib><creatorcontrib>Lee, Teck Sim</creatorcontrib><title>POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME</title><description>A power semiconductor package includes: a die carrier having first and second opposite sides; and first and second power semiconductor dies each having first and second power electrodes on opposite sides. The second power electrodes face and are electrically coupled to the first side of the carrier. A molded body at least partially encapsulates the dies and has a first and second opposite sides and lateral sides connecting the first and second sides. First and second power contacts and first and second control contacts are arranged laterally next to each other. The first power electrode of the first die is electrically coupled to the first power contact by a first electrical connector. The first power electrode of the second die is electrically coupled to the second power contact by a second electrical connector. A width of each power contact is at least four times the width of each control contact.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAP8A93DVIIdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB1DfHwd1FwAwq7OToFeTo7hnj6uSuEeLgqBDv6uvIwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvjQYCMDIxMDC3NLS1NHQ2PiVAEAFv0rKg</recordid><startdate>20240314</startdate><enddate>20240314</enddate><creator>Tommy Khoo, Chwee Pang</creator><creator>Unterhofer, Katrin</creator><creator>Schiele, Christian</creator><creator>Uredat, Patrick</creator><creator>Otremba, Ralf</creator><creator>Gan, Thai Kee</creator><creator>Lee, Teck Sim</creator><scope>EVB</scope></search><sort><creationdate>20240314</creationdate><title>POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME</title><author>Tommy Khoo, Chwee Pang ; Unterhofer, Katrin ; Schiele, Christian ; Uredat, Patrick ; Otremba, Ralf ; Gan, Thai Kee ; Lee, Teck Sim</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024087995A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Tommy Khoo, Chwee Pang</creatorcontrib><creatorcontrib>Unterhofer, Katrin</creatorcontrib><creatorcontrib>Schiele, Christian</creatorcontrib><creatorcontrib>Uredat, Patrick</creatorcontrib><creatorcontrib>Otremba, Ralf</creatorcontrib><creatorcontrib>Gan, Thai Kee</creatorcontrib><creatorcontrib>Lee, Teck Sim</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tommy Khoo, Chwee Pang</au><au>Unterhofer, Katrin</au><au>Schiele, Christian</au><au>Uredat, Patrick</au><au>Otremba, Ralf</au><au>Gan, Thai Kee</au><au>Lee, Teck Sim</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME</title><date>2024-03-14</date><risdate>2024</risdate><abstract>A power semiconductor package includes: a die carrier having first and second opposite sides; and first and second power semiconductor dies each having first and second power electrodes on opposite sides. The second power electrodes face and are electrically coupled to the first side of the carrier. A molded body at least partially encapsulates the dies and has a first and second opposite sides and lateral sides connecting the first and second sides. First and second power contacts and first and second control contacts are arranged laterally next to each other. The first power electrode of the first die is electrically coupled to the first power contact by a first electrical connector. The first power electrode of the second die is electrically coupled to the second power contact by a second electrical connector. A width of each power contact is at least four times the width of each control contact.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2024087995A1 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T01%3A07%3A09IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Tommy%20Khoo,%20Chwee%20Pang&rft.date=2024-03-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024087995A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |