FORMING OPERATION OF RESISTIVE MEMORY DEVICE

A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately perfo...

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Hauptverfasser: Cheng, Lung-Chi, Cheng, Ju-Chieh, Wang, Ping-Kun, Tseng, I-Hsien, Huang, Jun-Yao
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creator Cheng, Lung-Chi
Cheng, Ju-Chieh
Wang, Ping-Kun
Tseng, I-Hsien
Huang, Jun-Yao
description A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024087644A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024087644A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024087644A13</originalsourceid><addsrcrecordid>eNrjZNBx8w_y9fRzV_APcA1yDPH091Pwd1MIcg32DA7xDHNV8HX19Q-KVHBxDfN0duVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRiYGFuZmJiaOhsbEqQIAQa4mUA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FORMING OPERATION OF RESISTIVE MEMORY DEVICE</title><source>esp@cenet</source><creator>Cheng, Lung-Chi ; Cheng, Ju-Chieh ; Wang, Ping-Kun ; Tseng, I-Hsien ; Huang, Jun-Yao</creator><creatorcontrib>Cheng, Lung-Chi ; Cheng, Ju-Chieh ; Wang, Ping-Kun ; Tseng, I-Hsien ; Huang, Jun-Yao</creatorcontrib><description>A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240314&amp;DB=EPODOC&amp;CC=US&amp;NR=2024087644A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240314&amp;DB=EPODOC&amp;CC=US&amp;NR=2024087644A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Cheng, Lung-Chi</creatorcontrib><creatorcontrib>Cheng, Ju-Chieh</creatorcontrib><creatorcontrib>Wang, Ping-Kun</creatorcontrib><creatorcontrib>Tseng, I-Hsien</creatorcontrib><creatorcontrib>Huang, Jun-Yao</creatorcontrib><title>FORMING OPERATION OF RESISTIVE MEMORY DEVICE</title><description>A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNBx8w_y9fRzV_APcA1yDPH091Pwd1MIcg32DA7xDHNV8HX19Q-KVHBxDfN0duVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRiYGFuZmJiaOhsbEqQIAQa4mUA</recordid><startdate>20240314</startdate><enddate>20240314</enddate><creator>Cheng, Lung-Chi</creator><creator>Cheng, Ju-Chieh</creator><creator>Wang, Ping-Kun</creator><creator>Tseng, I-Hsien</creator><creator>Huang, Jun-Yao</creator><scope>EVB</scope></search><sort><creationdate>20240314</creationdate><title>FORMING OPERATION OF RESISTIVE MEMORY DEVICE</title><author>Cheng, Lung-Chi ; Cheng, Ju-Chieh ; Wang, Ping-Kun ; Tseng, I-Hsien ; Huang, Jun-Yao</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024087644A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Cheng, Lung-Chi</creatorcontrib><creatorcontrib>Cheng, Ju-Chieh</creatorcontrib><creatorcontrib>Wang, Ping-Kun</creatorcontrib><creatorcontrib>Tseng, I-Hsien</creatorcontrib><creatorcontrib>Huang, Jun-Yao</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cheng, Lung-Chi</au><au>Cheng, Ju-Chieh</au><au>Wang, Ping-Kun</au><au>Tseng, I-Hsien</au><au>Huang, Jun-Yao</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FORMING OPERATION OF RESISTIVE MEMORY DEVICE</title><date>2024-03-14</date><risdate>2024</risdate><abstract>A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.</abstract><oa>free_for_read</oa></addata></record>
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STATIC STORES
title FORMING OPERATION OF RESISTIVE MEMORY DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T08%3A48%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Cheng,%20Lung-Chi&rft.date=2024-03-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024087644A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true