Pixel Output Parasitic Capacitance Reduction and Predictive Settling Assist
Disclosed herein are electronic devices and image sensors containing pixel arrays, layouts of electrical signal lines for such pixel arrays, and methods of pixel read out operations, including row read operations, for such pixel arrays. Layouts are disclosed that have reduced sets of shielding or gr...
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creator | Yan, Hai Lee, Chiajen |
description | Disclosed herein are electronic devices and image sensors containing pixel arrays, layouts of electrical signal lines for such pixel arrays, and methods of pixel read out operations, including row read operations, for such pixel arrays. Layouts are disclosed that have reduced sets of shielding or ground lines. In some layouts, shielding ground lines are used only between pairs of adjacent pixel output signal lines (OSLs). Also disclosed is a method of using one OSL within a pair of adjacent pixel OSLs to provide settling assist of the pixel output signal on the other OSL of the adjacent pair of OSLs. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024064432A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024064432A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024064432A13</originalsourceid><addsrcrecordid>eNqNjLEKwjAQQLM4iPoPB85CTYN7KYrgYLE6lyM55SCkoXcRP98OfoDT48HjLc2l4w9FuBbNRaHDCYWVPbSY0bNi8gQ3CsUrjwkwBegmCjzrm6An1cjpBY0Ii67N4olRaPPjymxPx3t73lEeB5J5SIl0ePS2sq46OFfbZl__V30BKbM2Sw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Pixel Output Parasitic Capacitance Reduction and Predictive Settling Assist</title><source>esp@cenet</source><creator>Yan, Hai ; Lee, Chiajen</creator><creatorcontrib>Yan, Hai ; Lee, Chiajen</creatorcontrib><description>Disclosed herein are electronic devices and image sensors containing pixel arrays, layouts of electrical signal lines for such pixel arrays, and methods of pixel read out operations, including row read operations, for such pixel arrays. Layouts are disclosed that have reduced sets of shielding or ground lines. In some layouts, shielding ground lines are used only between pairs of adjacent pixel output signal lines (OSLs). Also disclosed is a method of using one OSL within a pair of adjacent pixel OSLs to provide settling assist of the pixel output signal on the other OSL of the adjacent pair of OSLs.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240222&DB=EPODOC&CC=US&NR=2024064432A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240222&DB=EPODOC&CC=US&NR=2024064432A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Yan, Hai</creatorcontrib><creatorcontrib>Lee, Chiajen</creatorcontrib><title>Pixel Output Parasitic Capacitance Reduction and Predictive Settling Assist</title><description>Disclosed herein are electronic devices and image sensors containing pixel arrays, layouts of electrical signal lines for such pixel arrays, and methods of pixel read out operations, including row read operations, for such pixel arrays. Layouts are disclosed that have reduced sets of shielding or ground lines. In some layouts, shielding ground lines are used only between pairs of adjacent pixel output signal lines (OSLs). Also disclosed is a method of using one OSL within a pair of adjacent pixel OSLs to provide settling assist of the pixel output signal on the other OSL of the adjacent pair of OSLs.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLEKwjAQQLM4iPoPB85CTYN7KYrgYLE6lyM55SCkoXcRP98OfoDT48HjLc2l4w9FuBbNRaHDCYWVPbSY0bNi8gQ3CsUrjwkwBegmCjzrm6An1cjpBY0Ii67N4olRaPPjymxPx3t73lEeB5J5SIl0ePS2sq46OFfbZl__V30BKbM2Sw</recordid><startdate>20240222</startdate><enddate>20240222</enddate><creator>Yan, Hai</creator><creator>Lee, Chiajen</creator><scope>EVB</scope></search><sort><creationdate>20240222</creationdate><title>Pixel Output Parasitic Capacitance Reduction and Predictive Settling Assist</title><author>Yan, Hai ; Lee, Chiajen</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024064432A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Yan, Hai</creatorcontrib><creatorcontrib>Lee, Chiajen</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yan, Hai</au><au>Lee, Chiajen</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Pixel Output Parasitic Capacitance Reduction and Predictive Settling Assist</title><date>2024-02-22</date><risdate>2024</risdate><abstract>Disclosed herein are electronic devices and image sensors containing pixel arrays, layouts of electrical signal lines for such pixel arrays, and methods of pixel read out operations, including row read operations, for such pixel arrays. Layouts are disclosed that have reduced sets of shielding or ground lines. In some layouts, shielding ground lines are used only between pairs of adjacent pixel output signal lines (OSLs). Also disclosed is a method of using one OSL within a pair of adjacent pixel OSLs to provide settling assist of the pixel output signal on the other OSL of the adjacent pair of OSLs.</abstract><oa>free_for_read</oa></addata></record> |
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title | Pixel Output Parasitic Capacitance Reduction and Predictive Settling Assist |
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