THREE-DIMENSIONAL MEMORY DEVICE, MEMORY SYSTEM, AND METHODS FOR FORMING THE SAME

THREE-DIMENSIONAL MEMORY DEVICE, MEMORY SYSTEM, AND METHODS FOR FORMING THE SAME

A 3D includes a memory array structure. The memory array structure includes a first memory array structure and a second memory array structure each having a plurality of conductive/dielectric layer pairs. The memory array structure also includes a staircase structure between the first memory array s...

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Hauptverfasser: Xia, Zhiliang, Yan, Bingjie, Xie, Jingtao, Zhou, Wenxi, Huo, Zongliang
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Sprache:eng
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INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator Xia, Zhiliang
Yan, Bingjie
Xie, Jingtao
Zhou, Wenxi
Huo, Zongliang
description A 3D includes a memory array structure. The memory array structure includes a first memory array structure and a second memory array structure each having a plurality of conductive/dielectric layer pairs. The memory array structure also includes a staircase structure between the first memory array structure and the second memory array structure. The staircase structure includes a first staircase zone and a second staircase zone. The first staircase zone includes at least one staircase, each including a plurality of stairs. The second staircase zone includes a bridge structure, and at least one other staircase over the bridge structure. The bridge structure connects the first memory array structure and the second memory array structure, the at least one other staircase each including a plurality of stairs. At least one stair in one or more of the at least one staircase is electrically connected to the bridge structure.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024032288A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024032288A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024032288A13</originalsourceid><addsrcrecordid>eNrjZAgI8QhyddV18fR19Qv29Pdz9FHwdfX1D4pUcHEN83R21YFxgyODQ1x9dRQc_VyAQiEe_i7BCm7-QSDs6-nnrhDi4aoQ7OjrysPAmpaYU5zKC6W5GZTdXEOcPXRTC_LjU4sLEpNT81JL4kODjQyMTAyMjYwsLBwNjYlTBQAfMS_H</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>THREE-DIMENSIONAL MEMORY DEVICE, MEMORY SYSTEM, AND METHODS FOR FORMING THE SAME</title><source>esp@cenet</source><creator>Xia, Zhiliang ; Yan, Bingjie ; Xie, Jingtao ; Zhou, Wenxi ; Huo, Zongliang</creator><creatorcontrib>Xia, Zhiliang ; Yan, Bingjie ; Xie, Jingtao ; Zhou, Wenxi ; Huo, Zongliang</creatorcontrib><description>A 3D includes a memory array structure. The memory array structure includes a first memory array structure and a second memory array structure each having a plurality of conductive/dielectric layer pairs. The memory array structure also includes a staircase structure between the first memory array structure and the second memory array structure. The staircase structure includes a first staircase zone and a second staircase zone. The first staircase zone includes at least one staircase, each including a plurality of stairs. The second staircase zone includes a bridge structure, and at least one other staircase over the bridge structure. The bridge structure connects the first memory array structure and the second memory array structure, the at least one other staircase each including a plurality of stairs. At least one stair in one or more of the at least one staircase is electrically connected to the bridge structure.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240125&amp;DB=EPODOC&amp;CC=US&amp;NR=2024032288A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240125&amp;DB=EPODOC&amp;CC=US&amp;NR=2024032288A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Xia, Zhiliang</creatorcontrib><creatorcontrib>Yan, Bingjie</creatorcontrib><creatorcontrib>Xie, Jingtao</creatorcontrib><creatorcontrib>Zhou, Wenxi</creatorcontrib><creatorcontrib>Huo, Zongliang</creatorcontrib><title>THREE-DIMENSIONAL MEMORY DEVICE, MEMORY SYSTEM, AND METHODS FOR FORMING THE SAME</title><description>A 3D includes a memory array structure. The memory array structure includes a first memory array structure and a second memory array structure each having a plurality of conductive/dielectric layer pairs. The memory array structure also includes a staircase structure between the first memory array structure and the second memory array structure. The staircase structure includes a first staircase zone and a second staircase zone. The first staircase zone includes at least one staircase, each including a plurality of stairs. The second staircase zone includes a bridge structure, and at least one other staircase over the bridge structure. The bridge structure connects the first memory array structure and the second memory array structure, the at least one other staircase each including a plurality of stairs. At least one stair in one or more of the at least one staircase is electrically connected to the bridge structure.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAgI8QhyddV18fR19Qv29Pdz9FHwdfX1D4pUcHEN83R21YFxgyODQ1x9dRQc_VyAQiEe_i7BCm7-QSDs6-nnrhDi4aoQ7OjrysPAmpaYU5zKC6W5GZTdXEOcPXRTC_LjU4sLEpNT81JL4kODjQyMTAyMjYwsLBwNjYlTBQAfMS_H</recordid><startdate>20240125</startdate><enddate>20240125</enddate><creator>Xia, Zhiliang</creator><creator>Yan, Bingjie</creator><creator>Xie, Jingtao</creator><creator>Zhou, Wenxi</creator><creator>Huo, Zongliang</creator><scope>EVB</scope></search><sort><creationdate>20240125</creationdate><title>THREE-DIMENSIONAL MEMORY DEVICE, MEMORY SYSTEM, AND METHODS FOR FORMING THE SAME</title><author>Xia, Zhiliang ; Yan, Bingjie ; Xie, Jingtao ; Zhou, Wenxi ; Huo, Zongliang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024032288A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Xia, Zhiliang</creatorcontrib><creatorcontrib>Yan, Bingjie</creatorcontrib><creatorcontrib>Xie, Jingtao</creatorcontrib><creatorcontrib>Zhou, Wenxi</creatorcontrib><creatorcontrib>Huo, Zongliang</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Xia, Zhiliang</au><au>Yan, Bingjie</au><au>Xie, Jingtao</au><au>Zhou, Wenxi</au><au>Huo, Zongliang</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>THREE-DIMENSIONAL MEMORY DEVICE, MEMORY SYSTEM, AND METHODS FOR FORMING THE SAME</title><date>2024-01-25</date><risdate>2024</risdate><abstract>A 3D includes a memory array structure. The memory array structure includes a first memory array structure and a second memory array structure each having a plurality of conductive/dielectric layer pairs. The memory array structure also includes a staircase structure between the first memory array structure and the second memory array structure. The staircase structure includes a first staircase zone and a second staircase zone. The first staircase zone includes at least one staircase, each including a plurality of stairs. The second staircase zone includes a bridge structure, and at least one other staircase over the bridge structure. The bridge structure connects the first memory array structure and the second memory array structure, the at least one other staircase each including a plurality of stairs. At least one stair in one or more of the at least one staircase is electrically connected to the bridge structure.</abstract><oa>free_for_read</oa></addata></record>
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STATIC STORES
title THREE-DIMENSIONAL MEMORY DEVICE, MEMORY SYSTEM, AND METHODS FOR FORMING THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T07%3A08%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Xia,%20Zhiliang&rft.date=2024-01-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024032288A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true