PACKAGE ARCHITECTURE OF SCALABLE COMPUTE WALL HAVING COMPUTE BRICKS WITH VERTICALLY STACKED DIES
Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies...
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| creator | Suthram, Sagar Deshpande, Nitin A Mallik, Debendra Sharma, Abhishek A Gomes, Wilfred Karhade, Omkar G Mahajan, Ravindranath Vithal Ranade, Pushkar Sharad |
| description | Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024006395A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024006395A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024006395A13</originalsourceid><addsrcrecordid>eNqNjEELgkAQRr10iOo_DHQOTCvoOI6ju7il7I5KJ5PYTlGC_X_yEJ07ffB475sH1wqpwJwBLSktTFJbhjIDR2gwMQxUnqpaGFo0BhQ2-pz_WGI1FQ5aLQoatqKnyFzAyXTKKaSa3TKY3fvH6FffXQTrjIXUxg-vzo9Df_NP_-5qF4XRLgwP8XGP2_g_6wM2xzQ4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PACKAGE ARCHITECTURE OF SCALABLE COMPUTE WALL HAVING COMPUTE BRICKS WITH VERTICALLY STACKED DIES</title><source>esp@cenet</source><creator>Suthram, Sagar ; Deshpande, Nitin A ; Mallik, Debendra ; Sharma, Abhishek A ; Gomes, Wilfred ; Karhade, Omkar G ; Mahajan, Ravindranath Vithal ; Ranade, Pushkar Sharad</creator><creatorcontrib>Suthram, Sagar ; Deshpande, Nitin A ; Mallik, Debendra ; Sharma, Abhishek A ; Gomes, Wilfred ; Karhade, Omkar G ; Mahajan, Ravindranath Vithal ; Ranade, Pushkar Sharad</creatorcontrib><description>Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240104&DB=EPODOC&CC=US&NR=2024006395A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240104&DB=EPODOC&CC=US&NR=2024006395A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Suthram, Sagar</creatorcontrib><creatorcontrib>Deshpande, Nitin A</creatorcontrib><creatorcontrib>Mallik, Debendra</creatorcontrib><creatorcontrib>Sharma, Abhishek A</creatorcontrib><creatorcontrib>Gomes, Wilfred</creatorcontrib><creatorcontrib>Karhade, Omkar G</creatorcontrib><creatorcontrib>Mahajan, Ravindranath Vithal</creatorcontrib><creatorcontrib>Ranade, Pushkar Sharad</creatorcontrib><title>PACKAGE ARCHITECTURE OF SCALABLE COMPUTE WALL HAVING COMPUTE BRICKS WITH VERTICALLY STACKED DIES</title><description>Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjEELgkAQRr10iOo_DHQOTCvoOI6ju7il7I5KJ5PYTlGC_X_yEJ07ffB475sH1wqpwJwBLSktTFJbhjIDR2gwMQxUnqpaGFo0BhQ2-pz_WGI1FQ5aLQoatqKnyFzAyXTKKaSa3TKY3fvH6FffXQTrjIXUxg-vzo9Df_NP_-5qF4XRLgwP8XGP2_g_6wM2xzQ4</recordid><startdate>20240104</startdate><enddate>20240104</enddate><creator>Suthram, Sagar</creator><creator>Deshpande, Nitin A</creator><creator>Mallik, Debendra</creator><creator>Sharma, Abhishek A</creator><creator>Gomes, Wilfred</creator><creator>Karhade, Omkar G</creator><creator>Mahajan, Ravindranath Vithal</creator><creator>Ranade, Pushkar Sharad</creator><scope>EVB</scope></search><sort><creationdate>20240104</creationdate><title>PACKAGE ARCHITECTURE OF SCALABLE COMPUTE WALL HAVING COMPUTE BRICKS WITH VERTICALLY STACKED DIES</title><author>Suthram, Sagar ; Deshpande, Nitin A ; Mallik, Debendra ; Sharma, Abhishek A ; Gomes, Wilfred ; Karhade, Omkar G ; Mahajan, Ravindranath Vithal ; Ranade, Pushkar Sharad</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024006395A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Suthram, Sagar</creatorcontrib><creatorcontrib>Deshpande, Nitin A</creatorcontrib><creatorcontrib>Mallik, Debendra</creatorcontrib><creatorcontrib>Sharma, Abhishek A</creatorcontrib><creatorcontrib>Gomes, Wilfred</creatorcontrib><creatorcontrib>Karhade, Omkar G</creatorcontrib><creatorcontrib>Mahajan, Ravindranath Vithal</creatorcontrib><creatorcontrib>Ranade, Pushkar Sharad</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Suthram, Sagar</au><au>Deshpande, Nitin A</au><au>Mallik, Debendra</au><au>Sharma, Abhishek A</au><au>Gomes, Wilfred</au><au>Karhade, Omkar G</au><au>Mahajan, Ravindranath Vithal</au><au>Ranade, Pushkar Sharad</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PACKAGE ARCHITECTURE OF SCALABLE COMPUTE WALL HAVING COMPUTE BRICKS WITH VERTICALLY STACKED DIES</title><date>2024-01-04</date><risdate>2024</risdate><abstract>Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | PACKAGE ARCHITECTURE OF SCALABLE COMPUTE WALL HAVING COMPUTE BRICKS WITH VERTICALLY STACKED DIES |
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