APPROACH FOR MANAGING NEAR-MEMORY PROCESSING COMMANDS FROM MULTIPLE PROCESSOR THREADS TO PREVENT INTERFERENCE AT NEAR-MEMORY PROCESSING ELEMENTS
An approach is provided for managing near-memory processing commands ("PIM commands") from multiple processor threads in a manner to prevent interference and maintain correctness at near-memory processing elements. A memory controller uses thread identification information and last command...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Aga, Shaizeen Alsop, Johnathan White, Laurent S |
description | An approach is provided for managing near-memory processing commands ("PIM commands") from multiple processor threads in a manner to prevent interference and maintain correctness at near-memory processing elements. A memory controller uses thread identification information and last command information to issue a PIM command sequence from a first processor thread, directed to a PIM-enabled memory element, while deferring the issuance of PIM command sequences from other processor threads, directed to the same PIM-enabled memory element. After the last PIM command in the PIM command sequence for the first processor thread has been issued, a PIM command sequence for another processor thread is issued, and so on. The approach allows multiple processor threads to concurrently issue fine grained PIM commands to the same PIM-enabled memory element without having to be aware of address-to-memory element mapping, and without having to coordinate with other threads. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024004653A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024004653A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024004653A13</originalsourceid><addsrcrecordid>eNqNjDEKwkAQRdNYiHqHAetATNR-WGeTQGY3zG4EqxBkrUQD8SAe2RW0FKw-vPf48-SJbSsWVQXaCjAaLGtTgiGUlImtnCB6Rc69sbIck4MDLZaBu8bXbUPfIh74Sgij9zZCOpLxUBtPoknIKAL0v66pIY65Wyazy3Cdwuqzi2StyasqDeO9D9M4nMMtPPrO5Vm-zbLtflfgpvivegGveUIY</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>APPROACH FOR MANAGING NEAR-MEMORY PROCESSING COMMANDS FROM MULTIPLE PROCESSOR THREADS TO PREVENT INTERFERENCE AT NEAR-MEMORY PROCESSING ELEMENTS</title><source>esp@cenet</source><creator>Aga, Shaizeen ; Alsop, Johnathan ; White, Laurent S</creator><creatorcontrib>Aga, Shaizeen ; Alsop, Johnathan ; White, Laurent S</creatorcontrib><description>An approach is provided for managing near-memory processing commands ("PIM commands") from multiple processor threads in a manner to prevent interference and maintain correctness at near-memory processing elements. A memory controller uses thread identification information and last command information to issue a PIM command sequence from a first processor thread, directed to a PIM-enabled memory element, while deferring the issuance of PIM command sequences from other processor threads, directed to the same PIM-enabled memory element. After the last PIM command in the PIM command sequence for the first processor thread has been issued, a PIM command sequence for another processor thread is issued, and so on. The approach allows multiple processor threads to concurrently issue fine grained PIM commands to the same PIM-enabled memory element without having to be aware of address-to-memory element mapping, and without having to coordinate with other threads.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240104&DB=EPODOC&CC=US&NR=2024004653A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240104&DB=EPODOC&CC=US&NR=2024004653A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Aga, Shaizeen</creatorcontrib><creatorcontrib>Alsop, Johnathan</creatorcontrib><creatorcontrib>White, Laurent S</creatorcontrib><title>APPROACH FOR MANAGING NEAR-MEMORY PROCESSING COMMANDS FROM MULTIPLE PROCESSOR THREADS TO PREVENT INTERFERENCE AT NEAR-MEMORY PROCESSING ELEMENTS</title><description>An approach is provided for managing near-memory processing commands ("PIM commands") from multiple processor threads in a manner to prevent interference and maintain correctness at near-memory processing elements. A memory controller uses thread identification information and last command information to issue a PIM command sequence from a first processor thread, directed to a PIM-enabled memory element, while deferring the issuance of PIM command sequences from other processor threads, directed to the same PIM-enabled memory element. After the last PIM command in the PIM command sequence for the first processor thread has been issued, a PIM command sequence for another processor thread is issued, and so on. The approach allows multiple processor threads to concurrently issue fine grained PIM commands to the same PIM-enabled memory element without having to be aware of address-to-memory element mapping, and without having to coordinate with other threads.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjDEKwkAQRdNYiHqHAetATNR-WGeTQGY3zG4EqxBkrUQD8SAe2RW0FKw-vPf48-SJbSsWVQXaCjAaLGtTgiGUlImtnCB6Rc69sbIck4MDLZaBu8bXbUPfIh74Sgij9zZCOpLxUBtPoknIKAL0v66pIY65Wyazy3Cdwuqzi2StyasqDeO9D9M4nMMtPPrO5Vm-zbLtflfgpvivegGveUIY</recordid><startdate>20240104</startdate><enddate>20240104</enddate><creator>Aga, Shaizeen</creator><creator>Alsop, Johnathan</creator><creator>White, Laurent S</creator><scope>EVB</scope></search><sort><creationdate>20240104</creationdate><title>APPROACH FOR MANAGING NEAR-MEMORY PROCESSING COMMANDS FROM MULTIPLE PROCESSOR THREADS TO PREVENT INTERFERENCE AT NEAR-MEMORY PROCESSING ELEMENTS</title><author>Aga, Shaizeen ; Alsop, Johnathan ; White, Laurent S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024004653A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Aga, Shaizeen</creatorcontrib><creatorcontrib>Alsop, Johnathan</creatorcontrib><creatorcontrib>White, Laurent S</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Aga, Shaizeen</au><au>Alsop, Johnathan</au><au>White, Laurent S</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>APPROACH FOR MANAGING NEAR-MEMORY PROCESSING COMMANDS FROM MULTIPLE PROCESSOR THREADS TO PREVENT INTERFERENCE AT NEAR-MEMORY PROCESSING ELEMENTS</title><date>2024-01-04</date><risdate>2024</risdate><abstract>An approach is provided for managing near-memory processing commands ("PIM commands") from multiple processor threads in a manner to prevent interference and maintain correctness at near-memory processing elements. A memory controller uses thread identification information and last command information to issue a PIM command sequence from a first processor thread, directed to a PIM-enabled memory element, while deferring the issuance of PIM command sequences from other processor threads, directed to the same PIM-enabled memory element. After the last PIM command in the PIM command sequence for the first processor thread has been issued, a PIM command sequence for another processor thread is issued, and so on. The approach allows multiple processor threads to concurrently issue fine grained PIM commands to the same PIM-enabled memory element without having to be aware of address-to-memory element mapping, and without having to coordinate with other threads.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2024004653A1 |
source | esp@cenet |
subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | APPROACH FOR MANAGING NEAR-MEMORY PROCESSING COMMANDS FROM MULTIPLE PROCESSOR THREADS TO PREVENT INTERFERENCE AT NEAR-MEMORY PROCESSING ELEMENTS |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T04%3A35%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Aga,%20Shaizeen&rft.date=2024-01-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024004653A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |