METHODS AND APPARATUS FOR TRANSFERRING DATA WITHIN HIERARCHICAL CACHE CIRCUITRY
Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to...
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| creator | KASERIDIS, Dimitrios BRUCE, Klas Magnus TURNER, Andrew John PUSDESRIS, Joseph Michael MAMEESH, Rania Hussein Hassan RAMAGIRI, Gurunath KIM, Ho-Seop JALAL, Jamshed |
| description | Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data. |
| format | Patent |
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The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231228&DB=EPODOC&CC=US&NR=2023418766A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231228&DB=EPODOC&CC=US&NR=2023418766A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KASERIDIS, Dimitrios</creatorcontrib><creatorcontrib>BRUCE, Klas Magnus</creatorcontrib><creatorcontrib>TURNER, Andrew John</creatorcontrib><creatorcontrib>PUSDESRIS, Joseph Michael</creatorcontrib><creatorcontrib>MAMEESH, Rania Hussein Hassan</creatorcontrib><creatorcontrib>RAMAGIRI, Gurunath</creatorcontrib><creatorcontrib>KIM, Ho-Seop</creatorcontrib><creatorcontrib>JALAL, Jamshed</creatorcontrib><title>METHODS AND APPARATUS FOR TRANSFERRING DATA WITHIN HIERARCHICAL CACHE CIRCUITRY</title><description>Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. 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The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.</abstract><oa>free_for_read</oa></addata></record> |
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| title | METHODS AND APPARATUS FOR TRANSFERRING DATA WITHIN HIERARCHICAL CACHE CIRCUITRY |
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