SEMICONDUCTOR DEVICES
A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure....
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Lee, Sohyun Yun, Kangoh Lee, Dongjin Lim, Junhee |
description | A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure. The first isolation structure includes an upper isolation pattern structure and a lower isolation pattern. The upper isolation pattern structure includes a first isolation pattern and a second isolation pattern covering a sidewall of the first isolation pattern. The lower isolation pattern is formed under and contacting the upper isolation pattern structure, and a width of the lower isolation pattern is greater than a width of the upper isolation pattern structure. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023402454A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023402454A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023402454A13</originalsourceid><addsrcrecordid>eNrjZBANdvX1dPb3cwl1DvEPUnBxDfN0dg3mYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkbGJgZGJqYmjobGxKkCACAlH-Y</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICES</title><source>esp@cenet</source><creator>Lee, Sohyun ; Yun, Kangoh ; Lee, Dongjin ; Lim, Junhee</creator><creatorcontrib>Lee, Sohyun ; Yun, Kangoh ; Lee, Dongjin ; Lim, Junhee</creatorcontrib><description>A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure. The first isolation structure includes an upper isolation pattern structure and a lower isolation pattern. The upper isolation pattern structure includes a first isolation pattern and a second isolation pattern covering a sidewall of the first isolation pattern. The lower isolation pattern is formed under and contacting the upper isolation pattern structure, and a width of the lower isolation pattern is greater than a width of the upper isolation pattern structure.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231214&DB=EPODOC&CC=US&NR=2023402454A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231214&DB=EPODOC&CC=US&NR=2023402454A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lee, Sohyun</creatorcontrib><creatorcontrib>Yun, Kangoh</creatorcontrib><creatorcontrib>Lee, Dongjin</creatorcontrib><creatorcontrib>Lim, Junhee</creatorcontrib><title>SEMICONDUCTOR DEVICES</title><description>A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure. The first isolation structure includes an upper isolation pattern structure and a lower isolation pattern. The upper isolation pattern structure includes a first isolation pattern and a second isolation pattern covering a sidewall of the first isolation pattern. The lower isolation pattern is formed under and contacting the upper isolation pattern structure, and a width of the lower isolation pattern is greater than a width of the upper isolation pattern structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBANdvX1dPb3cwl1DvEPUnBxDfN0dg3mYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkbGJgZGJqYmjobGxKkCACAlH-Y</recordid><startdate>20231214</startdate><enddate>20231214</enddate><creator>Lee, Sohyun</creator><creator>Yun, Kangoh</creator><creator>Lee, Dongjin</creator><creator>Lim, Junhee</creator><scope>EVB</scope></search><sort><creationdate>20231214</creationdate><title>SEMICONDUCTOR DEVICES</title><author>Lee, Sohyun ; Yun, Kangoh ; Lee, Dongjin ; Lim, Junhee</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023402454A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lee, Sohyun</creatorcontrib><creatorcontrib>Yun, Kangoh</creatorcontrib><creatorcontrib>Lee, Dongjin</creatorcontrib><creatorcontrib>Lim, Junhee</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee, Sohyun</au><au>Yun, Kangoh</au><au>Lee, Dongjin</au><au>Lim, Junhee</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICES</title><date>2023-12-14</date><risdate>2023</risdate><abstract>A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure. The first isolation structure includes an upper isolation pattern structure and a lower isolation pattern. The upper isolation pattern structure includes a first isolation pattern and a second isolation pattern covering a sidewall of the first isolation pattern. The lower isolation pattern is formed under and contacting the upper isolation pattern structure, and a width of the lower isolation pattern is greater than a width of the upper isolation pattern structure.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2023402454A1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR DEVICES |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T08%3A57%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Lee,%20Sohyun&rft.date=2023-12-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2023402454A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |