METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES
Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming a contact opening in an interlayer dielectric (ILD) layer disposed over an epitaxy source/drain region and forming a metal layer in the contact opening. The metal layer includes top po...
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| creator | CHANG, Chih-Wei YANG, Kai-Chieh CHENG, Ya-Yi TSAI, Ming-Hsing KO, Yu-Chen LIN, Wei-Jung WEN, Yu-Ting HUNG, Min-Hsiu |
| description | Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming a contact opening in an interlayer dielectric (ILD) layer disposed over an epitaxy source/drain region and forming a metal layer in the contact opening. The metal layer includes top portions, side portions, and a bottom portion, and a space is defined between the top portions of the metal layer. The method further includes performing a gradient metal removal process on the metal layer to enlarge the space, forming a sacrificial layer in the contact opening, recessing the sacrificial layer in the contact opening to expose a portion of the sidewall portions, removing the top portions and the exposed portion of the sidewall portions, removing the sacrificial layer, and forming a bulk metal layer on the bottom portion of the metal layer. |
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In some embodiments, the method includes forming a contact opening in an interlayer dielectric (ILD) layer disposed over an epitaxy source/drain region and forming a metal layer in the contact opening. The metal layer includes top portions, side portions, and a bottom portion, and a space is defined between the top portions of the metal layer. The method further includes performing a gradient metal removal process on the metal layer to enlarge the space, forming a sacrificial layer in the contact opening, recessing the sacrificial layer in the contact opening to expose a portion of the sidewall portions, removing the top portions and the exposed portion of the sidewall portions, removing the sacrificial layer, and forming a bulk metal layer on the bottom portion of the metal layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231130&DB=EPODOC&CC=US&NR=2023386914A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231130&DB=EPODOC&CC=US&NR=2023386914A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHANG, Chih-Wei</creatorcontrib><creatorcontrib>YANG, Kai-Chieh</creatorcontrib><creatorcontrib>CHENG, Ya-Yi</creatorcontrib><creatorcontrib>TSAI, Ming-Hsing</creatorcontrib><creatorcontrib>KO, Yu-Chen</creatorcontrib><creatorcontrib>LIN, Wei-Jung</creatorcontrib><creatorcontrib>WEN, Yu-Ting</creatorcontrib><creatorcontrib>HUNG, Min-Hsiu</creatorcontrib><title>METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES</title><description>Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming a contact opening in an interlayer dielectric (ILD) layer disposed over an epitaxy source/drain region and forming a metal layer in the contact opening. The metal layer includes top portions, side portions, and a bottom portion, and a space is defined between the top portions of the metal layer. The method further includes performing a gradient metal removal process on the metal layer to enlarge the space, forming a sacrificial layer in the contact opening, recessing the sacrificial layer in the contact opening to expose a portion of the sidewall portions, removing the top portions and the exposed portion of the sidewall portions, removing the sacrificial layer, and forming a bulk metal layer on the bottom portion of the metal layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDydQ3x8HcJVvB3U3DzD_L19HNXCHb19XT293MJdQ7xD1JwcQ3zdHZVCA4JAvJDg1yDeRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGRsbGFmaWhiaOhMXGqADj7KCc</recordid><startdate>20231130</startdate><enddate>20231130</enddate><creator>CHANG, Chih-Wei</creator><creator>YANG, Kai-Chieh</creator><creator>CHENG, Ya-Yi</creator><creator>TSAI, Ming-Hsing</creator><creator>KO, Yu-Chen</creator><creator>LIN, Wei-Jung</creator><creator>WEN, Yu-Ting</creator><creator>HUNG, Min-Hsiu</creator><scope>EVB</scope></search><sort><creationdate>20231130</creationdate><title>METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES</title><author>CHANG, Chih-Wei ; YANG, Kai-Chieh ; CHENG, Ya-Yi ; TSAI, Ming-Hsing ; KO, Yu-Chen ; LIN, Wei-Jung ; WEN, Yu-Ting ; HUNG, Min-Hsiu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023386914A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHANG, Chih-Wei</creatorcontrib><creatorcontrib>YANG, Kai-Chieh</creatorcontrib><creatorcontrib>CHENG, Ya-Yi</creatorcontrib><creatorcontrib>TSAI, Ming-Hsing</creatorcontrib><creatorcontrib>KO, Yu-Chen</creatorcontrib><creatorcontrib>LIN, Wei-Jung</creatorcontrib><creatorcontrib>WEN, Yu-Ting</creatorcontrib><creatorcontrib>HUNG, Min-Hsiu</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHANG, Chih-Wei</au><au>YANG, Kai-Chieh</au><au>CHENG, Ya-Yi</au><au>TSAI, Ming-Hsing</au><au>KO, Yu-Chen</au><au>LIN, Wei-Jung</au><au>WEN, Yu-Ting</au><au>HUNG, Min-Hsiu</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES</title><date>2023-11-30</date><risdate>2023</risdate><abstract>Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming a contact opening in an interlayer dielectric (ILD) layer disposed over an epitaxy source/drain region and forming a metal layer in the contact opening. The metal layer includes top portions, side portions, and a bottom portion, and a space is defined between the top portions of the metal layer. The method further includes performing a gradient metal removal process on the metal layer to enlarge the space, forming a sacrificial layer in the contact opening, recessing the sacrificial layer in the contact opening to expose a portion of the sidewall portions, removing the top portions and the exposed portion of the sidewall portions, removing the sacrificial layer, and forming a bulk metal layer on the bottom portion of the metal layer.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES |
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