INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured...
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| creator | YANG, Jung-Chan CHEN, Xiangdong LI, Johnny Chiahao ZHUANG, Hui-Zhong KAO, Jerry Chang Jui LI, Jian-Sing |
| description | A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured as a non-functional circuit. The first circuit includes a first pin and a second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes designating the first pin and the second pin as a first group of pins that are to be connected together. Placing the first cell layout by the APR tool includes connecting the first pin and the second pin in the first group of pins together thereby changing the first circuit to a second circuit. The second circuit is configured as a functional version of the first circuit. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023385504A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023385504A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023385504A13</originalsourceid><addsrcrecordid>eNrjZDD09AtxdQ9yDHF1UXD2DHIO9QxRcPRzUfB1DfHwd1Hwd1Nw8w_y9fRzVwjxcFUIdvR15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGxsYWpqYGJo6GxsSpAgDLgSco</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME</title><source>esp@cenet</source><creator>YANG, Jung-Chan ; CHEN, Xiangdong ; LI, Johnny Chiahao ; ZHUANG, Hui-Zhong ; KAO, Jerry Chang Jui ; LI, Jian-Sing</creator><creatorcontrib>YANG, Jung-Chan ; CHEN, Xiangdong ; LI, Johnny Chiahao ; ZHUANG, Hui-Zhong ; KAO, Jerry Chang Jui ; LI, Jian-Sing</creatorcontrib><description>A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured as a non-functional circuit. The first circuit includes a first pin and a second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes designating the first pin and the second pin as a first group of pins that are to be connected together. Placing the first cell layout by the APR tool includes connecting the first pin and the second pin in the first group of pins together thereby changing the first circuit to a second circuit. The second circuit is configured as a functional version of the first circuit.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231130&DB=EPODOC&CC=US&NR=2023385504A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231130&DB=EPODOC&CC=US&NR=2023385504A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YANG, Jung-Chan</creatorcontrib><creatorcontrib>CHEN, Xiangdong</creatorcontrib><creatorcontrib>LI, Johnny Chiahao</creatorcontrib><creatorcontrib>ZHUANG, Hui-Zhong</creatorcontrib><creatorcontrib>KAO, Jerry Chang Jui</creatorcontrib><creatorcontrib>LI, Jian-Sing</creatorcontrib><title>INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME</title><description>A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured as a non-functional circuit. The first circuit includes a first pin and a second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes designating the first pin and the second pin as a first group of pins that are to be connected together. Placing the first cell layout by the APR tool includes connecting the first pin and the second pin in the first group of pins together thereby changing the first circuit to a second circuit. The second circuit is configured as a functional version of the first circuit.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD09AtxdQ9yDHF1UXD2DHIO9QxRcPRzUfB1DfHwd1Hwd1Nw8w_y9fRzVwjxcFUIdvR15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGxsYWpqYGJo6GxsSpAgDLgSco</recordid><startdate>20231130</startdate><enddate>20231130</enddate><creator>YANG, Jung-Chan</creator><creator>CHEN, Xiangdong</creator><creator>LI, Johnny Chiahao</creator><creator>ZHUANG, Hui-Zhong</creator><creator>KAO, Jerry Chang Jui</creator><creator>LI, Jian-Sing</creator><scope>EVB</scope></search><sort><creationdate>20231130</creationdate><title>INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME</title><author>YANG, Jung-Chan ; CHEN, Xiangdong ; LI, Johnny Chiahao ; ZHUANG, Hui-Zhong ; KAO, Jerry Chang Jui ; LI, Jian-Sing</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023385504A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>YANG, Jung-Chan</creatorcontrib><creatorcontrib>CHEN, Xiangdong</creatorcontrib><creatorcontrib>LI, Johnny Chiahao</creatorcontrib><creatorcontrib>ZHUANG, Hui-Zhong</creatorcontrib><creatorcontrib>KAO, Jerry Chang Jui</creatorcontrib><creatorcontrib>LI, Jian-Sing</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YANG, Jung-Chan</au><au>CHEN, Xiangdong</au><au>LI, Johnny Chiahao</au><au>ZHUANG, Hui-Zhong</au><au>KAO, Jerry Chang Jui</au><au>LI, Jian-Sing</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME</title><date>2023-11-30</date><risdate>2023</risdate><abstract>A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured as a non-functional circuit. The first circuit includes a first pin and a second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes designating the first pin and the second pin as a first group of pins that are to be connected together. Placing the first cell layout by the APR tool includes connecting the first pin and the second pin in the first group of pins together thereby changing the first circuit to a second circuit. The second circuit is configured as a functional version of the first circuit.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
| title | INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME |
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