PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO PROTECT SHADOW STACKS

A processor of an aspect includes a decode unit to decode an instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine that an attempted change due to the instruction, to a shadow stack pointer of a sh...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SHANBHOGUE, VEDVYAS, BRANDT, JASON W, PATEL, BAIJU V, SAHITA, RAVI L, HUNTLEY, BARRY E
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator SHANBHOGUE, VEDVYAS
BRANDT, JASON W
PATEL, BAIJU V
SAHITA, RAVI L
HUNTLEY, BARRY E
description A processor of an aspect includes a decode unit to decode an instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine that an attempted change due to the instruction, to a shadow stack pointer of a shadow stack, would cause the shadow stack pointer to exceed an allowed range. The execution unit is also to take an exception in response to determining that the attempted change to the shadow stack pointer would cause the shadow stack pointer to exceed the allowed range. Other processors, methods, systems, and instructions are disclosed.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023376252A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023376252A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023376252A13</originalsourceid><addsrcrecordid>eNrjZHAPCPJ3dg0O9g8K1lHwdQ3x8HcBMoIjg0NcfYEMRz8XBU-_4JCgUOcQT3-_YIUQfwWgjhBX5xCFYA9HF_9wheAQR2fvYB4G1rTEnOJUXijNzaDs5hri7KGbWpAfn1pckJicmpdaEh8abGRgZGxsbmZkauRoaEycKgC89y3g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO PROTECT SHADOW STACKS</title><source>esp@cenet</source><creator>SHANBHOGUE, VEDVYAS ; BRANDT, JASON W ; PATEL, BAIJU V ; SAHITA, RAVI L ; HUNTLEY, BARRY E</creator><creatorcontrib>SHANBHOGUE, VEDVYAS ; BRANDT, JASON W ; PATEL, BAIJU V ; SAHITA, RAVI L ; HUNTLEY, BARRY E</creatorcontrib><description>A processor of an aspect includes a decode unit to decode an instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine that an attempted change due to the instruction, to a shadow stack pointer of a shadow stack, would cause the shadow stack pointer to exceed an allowed range. The execution unit is also to take an exception in response to determining that the attempted change to the shadow stack pointer would cause the shadow stack pointer to exceed the allowed range. Other processors, methods, systems, and instructions are disclosed.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231123&amp;DB=EPODOC&amp;CC=US&amp;NR=2023376252A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231123&amp;DB=EPODOC&amp;CC=US&amp;NR=2023376252A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHANBHOGUE, VEDVYAS</creatorcontrib><creatorcontrib>BRANDT, JASON W</creatorcontrib><creatorcontrib>PATEL, BAIJU V</creatorcontrib><creatorcontrib>SAHITA, RAVI L</creatorcontrib><creatorcontrib>HUNTLEY, BARRY E</creatorcontrib><title>PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO PROTECT SHADOW STACKS</title><description>A processor of an aspect includes a decode unit to decode an instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine that an attempted change due to the instruction, to a shadow stack pointer of a shadow stack, would cause the shadow stack pointer to exceed an allowed range. The execution unit is also to take an exception in response to determining that the attempted change to the shadow stack pointer would cause the shadow stack pointer to exceed the allowed range. Other processors, methods, systems, and instructions are disclosed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAPCPJ3dg0O9g8K1lHwdQ3x8HcBMoIjg0NcfYEMRz8XBU-_4JCgUOcQT3-_YIUQfwWgjhBX5xCFYA9HF_9wheAQR2fvYB4G1rTEnOJUXijNzaDs5hri7KGbWpAfn1pckJicmpdaEh8abGRgZGxsbmZkauRoaEycKgC89y3g</recordid><startdate>20231123</startdate><enddate>20231123</enddate><creator>SHANBHOGUE, VEDVYAS</creator><creator>BRANDT, JASON W</creator><creator>PATEL, BAIJU V</creator><creator>SAHITA, RAVI L</creator><creator>HUNTLEY, BARRY E</creator><scope>EVB</scope></search><sort><creationdate>20231123</creationdate><title>PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO PROTECT SHADOW STACKS</title><author>SHANBHOGUE, VEDVYAS ; BRANDT, JASON W ; PATEL, BAIJU V ; SAHITA, RAVI L ; HUNTLEY, BARRY E</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023376252A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SHANBHOGUE, VEDVYAS</creatorcontrib><creatorcontrib>BRANDT, JASON W</creatorcontrib><creatorcontrib>PATEL, BAIJU V</creatorcontrib><creatorcontrib>SAHITA, RAVI L</creatorcontrib><creatorcontrib>HUNTLEY, BARRY E</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHANBHOGUE, VEDVYAS</au><au>BRANDT, JASON W</au><au>PATEL, BAIJU V</au><au>SAHITA, RAVI L</au><au>HUNTLEY, BARRY E</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO PROTECT SHADOW STACKS</title><date>2023-11-23</date><risdate>2023</risdate><abstract>A processor of an aspect includes a decode unit to decode an instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine that an attempted change due to the instruction, to a shadow stack pointer of a shadow stack, would cause the shadow stack pointer to exceed an allowed range. The execution unit is also to take an exception in response to determining that the attempted change to the shadow stack pointer would cause the shadow stack pointer to exceed the allowed range. Other processors, methods, systems, and instructions are disclosed.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2023376252A1
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO PROTECT SHADOW STACKS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T16%3A11%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SHANBHOGUE,%20VEDVYAS&rft.date=2023-11-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2023376252A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true