SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements ou...
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| creator | Ould-Ahmed-Vall, Elmoustapha Macpherson, Mike Kim, SungYe George, Varghese Ranganathan, Vasanth Surti, Prasoonkumar Striramassarma, Lakshminarayanan Vemulapalli, Vikranth Koker, Altug Ray, Joydeep Hunter, JR., Arthur Sadler, William Andrei, Valentin Maiyuran, Subramaniam Appu, Abhishek Janus, Scott Garg, Ashutosh Harel, Yoav |
| description | Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements. |
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Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS |
| title | SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE |
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