METAL ROUTING THAT OVERLAPS NMOS AND PMOS REGIONS OF A TRANSISTOR

Embodiments described herein may be related to apparatuses, processes, and techniques for providing a metal routing layer zero (M0) track within a circuit structure that had a width that overlaps both PMOS and NMOS within the circuit structure. There may be three M0 routing tracks, with a first of t...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	WANG, Xinning, YEMENICIOGLU, Sukru, SCHENKER, Richard E, GHANI, Tahir
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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