METAL ROUTING THAT OVERLAPS NMOS AND PMOS REGIONS OF A TRANSISTOR

Embodiments described herein may be related to apparatuses, processes, and techniques for providing a metal routing layer zero (M0) track within a circuit structure that had a width that overlaps both PMOS and NMOS within the circuit structure. There may be three M0 routing tracks, with a first of t...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	WANG, Xinning, YEMENICIOGLU, Sukru, SCHENKER, Richard E, GHANI, Tahir
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	WANG, Xinning YEMENICIOGLU, Sukru SCHENKER, Richard E GHANI, Tahir
description	Embodiments described herein may be related to apparatuses, processes, and techniques for providing a metal routing layer zero (M0) track within a circuit structure that had a width that overlaps both PMOS and NMOS within the circuit structure. There may be three M0 routing tracks, with a first of the M0 routing tracks directly over PMOS, a second of the M0 routing tracks directly over NMOS, and a third of the M0 routing tracks over a portion separating PMOS and NMOS and overlapping both PMOS and NMOS. The wide second routing track will allow efficient electrical coupling between a device on the PMOS and a device on the NMOS. Other embodiments may be described and/or claimed.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023317602A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023317602A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023317602A13</originalsourceid><addsrcrecordid>eNrjZHD0dQ1x9FEI8g8N8fRzVwjxcAxR8A9zDfJxDAhW8PP1D1Zw9HNRCAAxglzdPf39ghX83RQcFUKCHP2CPYND_IN4GFjTEnOKU3mhNDeDsptriLOHbmpBfnxqcUFicmpeakl8aLCRgZGxsaG5mYGRo6ExcaoAhn4r3Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METAL ROUTING THAT OVERLAPS NMOS AND PMOS REGIONS OF A TRANSISTOR</title><source>esp@cenet</source><creator>WANG, Xinning ; YEMENICIOGLU, Sukru ; SCHENKER, Richard E ; GHANI, Tahir</creator><creatorcontrib>WANG, Xinning ; YEMENICIOGLU, Sukru ; SCHENKER, Richard E ; GHANI, Tahir</creatorcontrib><description>Embodiments described herein may be related to apparatuses, processes, and techniques for providing a metal routing layer zero (M0) track within a circuit structure that had a width that overlaps both PMOS and NMOS within the circuit structure. There may be three M0 routing tracks, with a first of the M0 routing tracks directly over PMOS, a second of the M0 routing tracks directly over NMOS, and a third of the M0 routing tracks over a portion separating PMOS and NMOS and overlapping both PMOS and NMOS. The wide second routing track will allow efficient electrical coupling between a device on the PMOS and a device on the NMOS. Other embodiments may be described and/or claimed.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231005&DB=EPODOC&CC=US&NR=2023317602A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231005&DB=EPODOC&CC=US&NR=2023317602A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WANG, Xinning</creatorcontrib><creatorcontrib>YEMENICIOGLU, Sukru</creatorcontrib><creatorcontrib>SCHENKER, Richard E</creatorcontrib><creatorcontrib>GHANI, Tahir</creatorcontrib><title>METAL ROUTING THAT OVERLAPS NMOS AND PMOS REGIONS OF A TRANSISTOR</title><description>Embodiments described herein may be related to apparatuses, processes, and techniques for providing a metal routing layer zero (M0) track within a circuit structure that had a width that overlaps both PMOS and NMOS within the circuit structure. There may be three M0 routing tracks, with a first of the M0 routing tracks directly over PMOS, a second of the M0 routing tracks directly over NMOS, and a third of the M0 routing tracks over a portion separating PMOS and NMOS and overlapping both PMOS and NMOS. The wide second routing track will allow efficient electrical coupling between a device on the PMOS and a device on the NMOS. Other embodiments may be described and/or claimed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHD0dQ1x9FEI8g8N8fRzVwjxcAxR8A9zDfJxDAhW8PP1D1Zw9HNRCAAxglzdPf39ghX83RQcFUKCHP2CPYND_IN4GFjTEnOKU3mhNDeDsptriLOHbmpBfnxqcUFicmpeakl8aLCRgZGxsaG5mYGRo6ExcaoAhn4r3Q</recordid><startdate>20231005</startdate><enddate>20231005</enddate><creator>WANG, Xinning</creator><creator>YEMENICIOGLU, Sukru</creator><creator>SCHENKER, Richard E</creator><creator>GHANI, Tahir</creator><scope>EVB</scope></search><sort><creationdate>20231005</creationdate><title>METAL ROUTING THAT OVERLAPS NMOS AND PMOS REGIONS OF A TRANSISTOR</title><author>WANG, Xinning ; YEMENICIOGLU, Sukru ; SCHENKER, Richard E ; GHANI, Tahir</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023317602A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>WANG, Xinning</creatorcontrib><creatorcontrib>YEMENICIOGLU, Sukru</creatorcontrib><creatorcontrib>SCHENKER, Richard E</creatorcontrib><creatorcontrib>GHANI, Tahir</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WANG, Xinning</au><au>YEMENICIOGLU, Sukru</au><au>SCHENKER, Richard E</au><au>GHANI, Tahir</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METAL ROUTING THAT OVERLAPS NMOS AND PMOS REGIONS OF A TRANSISTOR</title><date>2023-10-05</date><risdate>2023</risdate><abstract>Embodiments described herein may be related to apparatuses, processes, and techniques for providing a metal routing layer zero (M0) track within a circuit structure that had a width that overlaps both PMOS and NMOS within the circuit structure. There may be three M0 routing tracks, with a first of the M0 routing tracks directly over PMOS, a second of the M0 routing tracks directly over NMOS, and a third of the M0 routing tracks over a portion separating PMOS and NMOS and overlapping both PMOS and NMOS. The wide second routing track will allow efficient electrical coupling between a device on the PMOS and a device on the NMOS. Other embodiments may be described and/or claimed.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US2023317602A1
source	esp@cenet
subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	METAL ROUTING THAT OVERLAPS NMOS AND PMOS REGIONS OF A TRANSISTOR
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T15%3A02%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WANG,%20Xinning&rft.date=2023-10-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2023317602A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true