DIODE AND METHOD OF MAKING THE SAME

A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherei...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Caruso, Anthony, Usenko, Alex, Bellinger, Steven
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Caruso, Anthony
Usenko, Alex
Bellinger, Steven
description A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherein said second silicon wafer is CZ-grown P-doped with orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma, followed by cleaning the respective first and second silicon wafers. The wafers are then HF treated to yield respective first and second cleaned wafers, the first cleaned wafer is positioned into a first furnace and the second cleaned wafer is positioned into a second furnace, wherein the first and second furnaces are not unitary. Next is annealing the respective first and second cleaned wafers in a reducing atmosphere to yield respective first and second respective out-diffused gradient wafers, followed by bonding together respective first and second heat-treated wafers to yield a mated and/or bonded four-layer substrate having a first heavy doped n-type layer, a second gradient doped n-type layer, a third gradient doped p-type layer, and a fourth heavy doped p-type layer.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023299210A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023299210A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023299210A13</originalsourceid><addsrcrecordid>eNrjZFB28fR3cVVw9HNR8HUN8fB3UfB3U_B19Pb0c1cI8XBVCHb0deVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRsZGlpZGhgaOhsbEqQIAoVEjBg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DIODE AND METHOD OF MAKING THE SAME</title><source>esp@cenet</source><creator>Caruso, Anthony ; Usenko, Alex ; Bellinger, Steven</creator><creatorcontrib>Caruso, Anthony ; Usenko, Alex ; Bellinger, Steven</creatorcontrib><description>A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherein said second silicon wafer is CZ-grown P-doped with orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma, followed by cleaning the respective first and second silicon wafers. The wafers are then HF treated to yield respective first and second cleaned wafers, the first cleaned wafer is positioned into a first furnace and the second cleaned wafer is positioned into a second furnace, wherein the first and second furnaces are not unitary. Next is annealing the respective first and second cleaned wafers in a reducing atmosphere to yield respective first and second respective out-diffused gradient wafers, followed by bonding together respective first and second heat-treated wafers to yield a mated and/or bonded four-layer substrate having a first heavy doped n-type layer, a second gradient doped n-type layer, a third gradient doped p-type layer, and a fourth heavy doped p-type layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230921&amp;DB=EPODOC&amp;CC=US&amp;NR=2023299210A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230921&amp;DB=EPODOC&amp;CC=US&amp;NR=2023299210A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Caruso, Anthony</creatorcontrib><creatorcontrib>Usenko, Alex</creatorcontrib><creatorcontrib>Bellinger, Steven</creatorcontrib><title>DIODE AND METHOD OF MAKING THE SAME</title><description>A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherein said second silicon wafer is CZ-grown P-doped with orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma, followed by cleaning the respective first and second silicon wafers. The wafers are then HF treated to yield respective first and second cleaned wafers, the first cleaned wafer is positioned into a first furnace and the second cleaned wafer is positioned into a second furnace, wherein the first and second furnaces are not unitary. Next is annealing the respective first and second cleaned wafers in a reducing atmosphere to yield respective first and second respective out-diffused gradient wafers, followed by bonding together respective first and second heat-treated wafers to yield a mated and/or bonded four-layer substrate having a first heavy doped n-type layer, a second gradient doped n-type layer, a third gradient doped p-type layer, and a fourth heavy doped p-type layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFB28fR3cVVw9HNR8HUN8fB3UfB3U_B19Pb0c1cI8XBVCHb0deVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRsZGlpZGhgaOhsbEqQIAoVEjBg</recordid><startdate>20230921</startdate><enddate>20230921</enddate><creator>Caruso, Anthony</creator><creator>Usenko, Alex</creator><creator>Bellinger, Steven</creator><scope>EVB</scope></search><sort><creationdate>20230921</creationdate><title>DIODE AND METHOD OF MAKING THE SAME</title><author>Caruso, Anthony ; Usenko, Alex ; Bellinger, Steven</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023299210A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Caruso, Anthony</creatorcontrib><creatorcontrib>Usenko, Alex</creatorcontrib><creatorcontrib>Bellinger, Steven</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Caruso, Anthony</au><au>Usenko, Alex</au><au>Bellinger, Steven</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DIODE AND METHOD OF MAKING THE SAME</title><date>2023-09-21</date><risdate>2023</risdate><abstract>A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherein said second silicon wafer is CZ-grown P-doped with orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma, followed by cleaning the respective first and second silicon wafers. The wafers are then HF treated to yield respective first and second cleaned wafers, the first cleaned wafer is positioned into a first furnace and the second cleaned wafer is positioned into a second furnace, wherein the first and second furnaces are not unitary. Next is annealing the respective first and second cleaned wafers in a reducing atmosphere to yield respective first and second respective out-diffused gradient wafers, followed by bonding together respective first and second heat-treated wafers to yield a mated and/or bonded four-layer substrate having a first heavy doped n-type layer, a second gradient doped n-type layer, a third gradient doped p-type layer, and a fourth heavy doped p-type layer.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2023299210A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title DIODE AND METHOD OF MAKING THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T06%3A34%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Caruso,%20Anthony&rft.date=2023-09-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2023299210A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true