FETCH REQUEST ARBITER

Driving address translations in a microprocessor system by sending a rejected Lx+1 cache request from a first set of caches of a first level Lx to a central request unit, transferring an Lx+1 cache request having a translation of a virtual address into a physical address stored in a first buffer, fr...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Koehler, Thomas G, Deutschle, Joerg, Hinrichs, Willm, Kaltenbach, Markus, Friedmann, Simon Hermann
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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