TIMING SEQUENCE GENERATION CIRCUIT

TIMING SEQUENCE GENERATION CIRCUIT

In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Jouanneau, Thomas
Format: Patent
Sprache:eng
Schlagworte:
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Jouanneau, Thomas
description In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023291395A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023291395A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023291395A13</originalsourceid><addsrcrecordid>eNrjZFAK8fT19HNXCHYNDHX1c3ZVcHf1cw1yDPH091Nw9gxyDvUM4WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGxkaWhsaWpo6GxsSpAgDOlSOF</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>TIMING SEQUENCE GENERATION CIRCUIT</title><source>esp@cenet</source><creator>Jouanneau, Thomas</creator><creatorcontrib>Jouanneau, Thomas</creatorcontrib><description>In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register</description><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230914&amp;DB=EPODOC&amp;CC=US&amp;NR=2023291395A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230914&amp;DB=EPODOC&amp;CC=US&amp;NR=2023291395A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Jouanneau, Thomas</creatorcontrib><title>TIMING SEQUENCE GENERATION CIRCUIT</title><description>In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAK8fT19HNXCHYNDHX1c3ZVcHf1cw1yDPH091Nw9gxyDvUM4WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGxkaWhsaWpo6GxsSpAgDOlSOF</recordid><startdate>20230914</startdate><enddate>20230914</enddate><creator>Jouanneau, Thomas</creator><scope>EVB</scope></search><sort><creationdate>20230914</creationdate><title>TIMING SEQUENCE GENERATION CIRCUIT</title><author>Jouanneau, Thomas</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023291395A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>Jouanneau, Thomas</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jouanneau, Thomas</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TIMING SEQUENCE GENERATION CIRCUIT</title><date>2023-09-14</date><risdate>2023</risdate><abstract>In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2023291395A1
source esp@cenet
subjects AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title TIMING SEQUENCE GENERATION CIRCUIT
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-23T04%3A05%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Jouanneau,%20Thomas&rft.date=2023-09-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2023291395A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true