APPARATUS, METHOD AND SYSTEM TO IMPLEMENT A DUAL VDM SCHEME ON A THREE-DIMENSIONAL MEMORY ARCHITECTURE

An apparatus, system and method. The apparatus is to be coupled to a memory array of a memory device. The apparatus, in response to a determination of a set command to be implemented on first memory cells of the memory array, is to control an execution of a set pre-read operation on the first memory cells by causing application, by a voltage source, of a first demarcation voltage VDM0 across each of the first memory cells during a set pre-read time period. The apparatus is further to, in response to a determination of a reset command to be implemented on second memory cells of the memory array, control an execution of a reset pre-read operation on the second memory cells by causing application, by the voltage source, of a second demarcation voltage VDM3 across each of the second memory cells during a reset pre-read time period, wherein the set pre-read time period and the reset pre-read time period do not overlap, the voltage source to supply a single voltage value at any given time.