OVERLAY LAYER HARDWARE UNIT FOR NETWORK OF PROCESSOR CORES
Methods and systems for executing an application data flow graph on a set of computational nodes are disclosed. The computational nodes can each include a programmable controller from a set of programmable controllers, a memory from a set of memories, a network interface unit from a set of network i...
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| creator | Aydonat, Utku Chin, S. Alexander Maksimovic, Djordje Vasiljevic, Jasmina Bajic, Ljubisa Matosevic, Ivan Capalija, Davor |
| description | Methods and systems for executing an application data flow graph on a set of computational nodes are disclosed. The computational nodes can each include a programmable controller from a set of programmable controllers, a memory from a set of memories, a network interface unit from a set of network interface units, and an endpoint from a set of endpoints. A disclosed method comprises configuring the programmable controllers with instructions. The method also comprises independently and asynchronously executing the instructions using the set of programmable controllers in response to a set of events exchanged between the programmable controllers themselves, between the programmable controllers and the network interface units, and between the programmable controllers and the set of endpoints. The method also comprises transitioning data in the set of memories on the computational nodes in accordance with the application data flow graph and in response to the execution of the instructions. |
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The method also comprises independently and asynchronously executing the instructions using the set of programmable controllers in response to a set of events exchanged between the programmable controllers themselves, between the programmable controllers and the network interface units, and between the programmable controllers and the set of endpoints. The method also comprises transitioning data in the set of memories on the computational nodes in accordance with the application data flow graph and in response to the execution of the instructions.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDyD3MN8nGMVABi1yAFD8cgl3DHIFeFUD_PEAU3_yAFP9eQcP8gbwV_N4WAIH9n1-BgoKCzf5BrMA8Da1piTnEqL5TmZlB2cw1x9tBNLciPTy0uSExOzUstiQ8NNjIwMjayMDQ0NXU0NCZOFQBurCoe</recordid><startdate>20230907</startdate><enddate>20230907</enddate><creator>Aydonat, Utku</creator><creator>Chin, S. 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Alexander</creatorcontrib><creatorcontrib>Maksimovic, Djordje</creatorcontrib><creatorcontrib>Vasiljevic, Jasmina</creatorcontrib><creatorcontrib>Bajic, Ljubisa</creatorcontrib><creatorcontrib>Matosevic, Ivan</creatorcontrib><creatorcontrib>Capalija, Davor</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Aydonat, Utku</au><au>Chin, S. Alexander</au><au>Maksimovic, Djordje</au><au>Vasiljevic, Jasmina</au><au>Bajic, Ljubisa</au><au>Matosevic, Ivan</au><au>Capalija, Davor</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>OVERLAY LAYER HARDWARE UNIT FOR NETWORK OF PROCESSOR CORES</title><date>2023-09-07</date><risdate>2023</risdate><abstract>Methods and systems for executing an application data flow graph on a set of computational nodes are disclosed. The computational nodes can each include a programmable controller from a set of programmable controllers, a memory from a set of memories, a network interface unit from a set of network interface units, and an endpoint from a set of endpoints. A disclosed method comprises configuring the programmable controllers with instructions. The method also comprises independently and asynchronously executing the instructions using the set of programmable controllers in response to a set of events exchanged between the programmable controllers themselves, between the programmable controllers and the network interface units, and between the programmable controllers and the set of endpoints. The method also comprises transitioning data in the set of memories on the computational nodes in accordance with the application data flow graph and in response to the execution of the instructions.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | OVERLAY LAYER HARDWARE UNIT FOR NETWORK OF PROCESSOR CORES |
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