INTERCONNECTED MEMORY GRID WITH BYPASSABLE UNITS
A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network...
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| creator | NAGAR, Eyal SCHNEIDER, Ron RAZ, Elad TAYARI, Ilan LOSSIN, Yoav |
| description | A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypassable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto. |
| format | Patent |
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wherein configuring the interconnected memory comprises: identifying a bypassable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDw9AtxDXL29_NzdQ5xdVHwdfX1D4pUcA_ydFEI9wzxUHCKDHAMDnZ08nFVCPXzDAnmYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkbGRubG5sZmjobGxKkCAORtJ3o</recordid><startdate>20230831</startdate><enddate>20230831</enddate><creator>NAGAR, Eyal</creator><creator>SCHNEIDER, Ron</creator><creator>RAZ, Elad</creator><creator>TAYARI, Ilan</creator><creator>LOSSIN, Yoav</creator><scope>EVB</scope></search><sort><creationdate>20230831</creationdate><title>INTERCONNECTED MEMORY GRID WITH BYPASSABLE UNITS</title><author>NAGAR, Eyal ; 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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | INTERCONNECTED MEMORY GRID WITH BYPASSABLE UNITS |
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