DUAL DUTY CYCLE CORRECTION LOOP FOR A SERIALIZER/DESERIALIZER (SERDES) TRANSMITTER OUTPUT
Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica p...
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Sprache: | eng |
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