CLOCK DATA RECOVERY (CDR) WITH MULTIPLE PROPORTIONAL PATH CONTROLS

A digital clock data recovery circuit including: a first vote circuit connected at an output of a first deserializer and configured to generate an even up/down signal based on even deserialized signals from the first deserializer; a first digital to analog converter (DAC) connected at an output of t...

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Bibliographische Detailangaben

Hauptverfasser:	Song, Younghoon, Jose, Anup P
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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