CONFIGURATION OF ONE OR MORE MEMORY PROCESSING UNITS
Disclosed embodiments include a computational memory system. The computational memory system includes a master controller configured to receive a configuration function from a host CPU and convert the received configuration function into one or more lower level configuration functions. The computati...
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| creator | MAYER-WOLF, Ilan DAYAN, Gal SRETER, Hillel HILLEL, Eliad |
| description | Disclosed embodiments include a computational memory system. The computational memory system includes a master controller configured to receive a configuration function from a host CPU and convert the received configuration function into one or more lower level configuration functions. The computational memory system also includes at least one computational memory chip, wherein the at least one computational memory chip includes a plurality of processor subunits and a plurality of memory banks formed on a common substrate. The master controller is adapted to configure the at least one computational memory chip using the one or more lower level configuration functions. |
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The computational memory system includes a master controller configured to receive a configuration function from a host CPU and convert the received configuration function into one or more lower level configuration functions. The computational memory system also includes at least one computational memory chip, wherein the at least one computational memory chip includes a plurality of processor subunits and a plurality of memory banks formed on a common substrate. The master controller is adapted to configure the at least one computational memory chip using the one or more lower level configuration functions.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230803&DB=EPODOC&CC=US&NR=2023244619A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230803&DB=EPODOC&CC=US&NR=2023244619A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MAYER-WOLF, Ilan</creatorcontrib><creatorcontrib>DAYAN, Gal</creatorcontrib><creatorcontrib>SRETER, Hillel</creatorcontrib><creatorcontrib>HILLEL, Eliad</creatorcontrib><title>CONFIGURATION OF ONE OR MORE MEMORY PROCESSING UNITS</title><description>Disclosed embodiments include a computational memory system. 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The computational memory system includes a master controller configured to receive a configuration function from a host CPU and convert the received configuration function into one or more lower level configuration functions. The computational memory system also includes at least one computational memory chip, wherein the at least one computational memory chip includes a plurality of processor subunits and a plurality of memory banks formed on a common substrate. The master controller is adapted to configure the at least one computational memory chip using the one or more lower level configuration functions.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | CONFIGURATION OF ONE OR MORE MEMORY PROCESSING UNITS |
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