SEMICONDUCTOR PACKAGE
A semiconductor package according to an embodiment includes a first insulating layer including a through hole; an insulating member disposed in the through hole of the first insulating layer; a first electrode layer disposed on the insulating member; a second insulating layer disposed on the first e...
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| creator | NAM, Sang Hyuck KWON, Myung Jae PARK, Jin Hyoung |
| description | A semiconductor package according to an embodiment includes a first insulating layer including a through hole; an insulating member disposed in the through hole of the first insulating layer; a first electrode layer disposed on the insulating member; a second insulating layer disposed on the first electrode layer; and a first through electrode passing through the second insulating layer, wherein the first through electrode overlaps the first electrode layer and the insulating member in a vertical direction. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023232544A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023232544A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023232544A13</originalsourceid><addsrcrecordid>eNrjZBANdvX1dPb3cwl1DvEPUghwdPZ2dHflYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkbGQGhqYuJoaEycKgAX6h_R</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR PACKAGE</title><source>esp@cenet</source><creator>NAM, Sang Hyuck ; KWON, Myung Jae ; PARK, Jin Hyoung</creator><creatorcontrib>NAM, Sang Hyuck ; KWON, Myung Jae ; PARK, Jin Hyoung</creatorcontrib><description>A semiconductor package according to an embodiment includes a first insulating layer including a through hole; an insulating member disposed in the through hole of the first insulating layer; a first electrode layer disposed on the insulating member; a second insulating layer disposed on the first electrode layer; and a first through electrode passing through the second insulating layer, wherein the first through electrode overlaps the first electrode layer and the insulating member in a vertical direction.</description><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230720&DB=EPODOC&CC=US&NR=2023232544A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230720&DB=EPODOC&CC=US&NR=2023232544A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NAM, Sang Hyuck</creatorcontrib><creatorcontrib>KWON, Myung Jae</creatorcontrib><creatorcontrib>PARK, Jin Hyoung</creatorcontrib><title>SEMICONDUCTOR PACKAGE</title><description>A semiconductor package according to an embodiment includes a first insulating layer including a through hole; an insulating member disposed in the through hole of the first insulating layer; a first electrode layer disposed on the insulating member; a second insulating layer disposed on the first electrode layer; and a first through electrode passing through the second insulating layer, wherein the first through electrode overlaps the first electrode layer and the insulating member in a vertical direction.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBANdvX1dPb3cwl1DvEPUghwdPZ2dHflYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkbGQGhqYuJoaEycKgAX6h_R</recordid><startdate>20230720</startdate><enddate>20230720</enddate><creator>NAM, Sang Hyuck</creator><creator>KWON, Myung Jae</creator><creator>PARK, Jin Hyoung</creator><scope>EVB</scope></search><sort><creationdate>20230720</creationdate><title>SEMICONDUCTOR PACKAGE</title><author>NAM, Sang Hyuck ; KWON, Myung Jae ; PARK, Jin Hyoung</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023232544A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>NAM, Sang Hyuck</creatorcontrib><creatorcontrib>KWON, Myung Jae</creatorcontrib><creatorcontrib>PARK, Jin Hyoung</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NAM, Sang Hyuck</au><au>KWON, Myung Jae</au><au>PARK, Jin Hyoung</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE</title><date>2023-07-20</date><risdate>2023</risdate><abstract>A semiconductor package according to an embodiment includes a first insulating layer including a through hole; an insulating member disposed in the through hole of the first insulating layer; a first electrode layer disposed on the insulating member; a second insulating layer disposed on the first electrode layer; and a first through electrode passing through the second insulating layer, wherein the first through electrode overlaps the first electrode layer and the insulating member in a vertical direction.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS |
| title | SEMICONDUCTOR PACKAGE |
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