HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, while maintaining flexibility for additional computations t...

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Hauptverfasser:	Rajamani, Kannan, Zivkovic, Zoran, Azadet, Kameran, Smith, Thomas
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	Rajamani, Kannan Zivkovic, Zoran Azadet, Kameran Smith, Thomas
description	Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, while maintaining flexibility for additional computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.
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title	HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE
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