RELAXED INVALIDATION FOR CACHE COHERENCE

Methods, systems, and devices maintain state information in a shadow tag memory for a plurality of cachelines in each of a plurality of private caches, with each of the private caches being associated with a corresponding one of multiple processing cores. One or more cache probes are generated based...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Nakra, Tarun, Arunkumar, Akhil, Kazakov, Maxim V, Nemlekar, Milind N
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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