MULTI-STAGE ERASE OPERATION OF MEMORY CELLS IN A MEMORY SUB-SYSTEM
Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the me...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Lu, Ching-Huang Dong, Yingda Ratnam, Sampath K |
| description | Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023195328A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023195328A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023195328A13</originalsourceid><addsrcrecordid>eNrjZHDyDfUJ8dQNDnF0d1VwDXIMdlXwDwDSIZ7-fgr-bgq-rr7-QZEKzq4-PsEKnn4KjjCR4FAn3eDI4BBXXx4G1rTEnOJUXijNzaDs5hri7KGbWpAfn1pckJicmpdaEh8abGRgZGxoaWpsZOFoaEycKgCoPCwe</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MULTI-STAGE ERASE OPERATION OF MEMORY CELLS IN A MEMORY SUB-SYSTEM</title><source>esp@cenet</source><creator>Lu, Ching-Huang ; Dong, Yingda ; Ratnam, Sampath K</creator><creatorcontrib>Lu, Ching-Huang ; Dong, Yingda ; Ratnam, Sampath K</creatorcontrib><description>Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230622&DB=EPODOC&CC=US&NR=2023195328A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230622&DB=EPODOC&CC=US&NR=2023195328A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lu, Ching-Huang</creatorcontrib><creatorcontrib>Dong, Yingda</creatorcontrib><creatorcontrib>Ratnam, Sampath K</creatorcontrib><title>MULTI-STAGE ERASE OPERATION OF MEMORY CELLS IN A MEMORY SUB-SYSTEM</title><description>Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDyDfUJ8dQNDnF0d1VwDXIMdlXwDwDSIZ7-fgr-bgq-rr7-QZEKzq4-PsEKnn4KjjCR4FAn3eDI4BBXXx4G1rTEnOJUXijNzaDs5hri7KGbWpAfn1pckJicmpdaEh8abGRgZGxoaWpsZOFoaEycKgCoPCwe</recordid><startdate>20230622</startdate><enddate>20230622</enddate><creator>Lu, Ching-Huang</creator><creator>Dong, Yingda</creator><creator>Ratnam, Sampath K</creator><scope>EVB</scope></search><sort><creationdate>20230622</creationdate><title>MULTI-STAGE ERASE OPERATION OF MEMORY CELLS IN A MEMORY SUB-SYSTEM</title><author>Lu, Ching-Huang ; Dong, Yingda ; Ratnam, Sampath K</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023195328A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Lu, Ching-Huang</creatorcontrib><creatorcontrib>Dong, Yingda</creatorcontrib><creatorcontrib>Ratnam, Sampath K</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lu, Ching-Huang</au><au>Dong, Yingda</au><au>Ratnam, Sampath K</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MULTI-STAGE ERASE OPERATION OF MEMORY CELLS IN A MEMORY SUB-SYSTEM</title><date>2023-06-22</date><risdate>2023</risdate><abstract>Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2023195328A1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | MULTI-STAGE ERASE OPERATION OF MEMORY CELLS IN A MEMORY SUB-SYSTEM |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T13%3A33%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Lu,%20Ching-Huang&rft.date=2023-06-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2023195328A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |