SOLID-STATE IMAGING ELEMENT

SOLID-STATE IMAGING ELEMENT

Solid-state imaging elements are disclosed. In one example, an upstream circuit sequentially generates a predetermined reset level and a signal level corresponding to an exposure amount, and causes first and second capacitive elements to hold the reset level and the signal level. A selection circuit...

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Hauptverfasser: Asakura, Luonghung, Inada, Yoshiaki
Format: Patent
Sprache:eng
Schlagworte:
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
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creator Asakura, Luonghung
Inada, Yoshiaki
description Solid-state imaging elements are disclosed. In one example, an upstream circuit sequentially generates a predetermined reset level and a signal level corresponding to an exposure amount, and causes first and second capacitive elements to hold the reset level and the signal level. A selection circuit sequentially connects one of the capacitive elements to a predetermined downstream node, disconnects both capacitive elements from the downstream node, and connects the other capacitive element to the downstream node. A downstream reset transistor initializes a level of the downstream node when both capacitive elements are disconnected from the downstream node. A downstream circuit sequentially reads the reset level and the signal level from the first and second capacitive elements via the downstream node and outputs the reset level and the signal level.
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subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
title SOLID-STATE IMAGING ELEMENT
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