THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
A three-dimensional semiconductor memory device includes: a stack structure including a ground selection line, first word lines, second word lines, and a string selection line, which are sequentially stacked on a substrate; vertical channel structures penetrating the stack structure and arranged to...
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creator | KANAMORI, Kohji HAN, Jeehoon KIM, Seung Yoon |
description | A three-dimensional semiconductor memory device includes: a stack structure including a ground selection line, first word lines, second word lines, and a string selection line, which are sequentially stacked on a substrate; vertical channel structures penetrating the stack structure and arranged to form a plurality of columns; a lower separation structure crossing a lower portion of the stack structure in a first direction and dividing the ground selection line along a second direction intersecting the first direction; and first and second upper separation structures crossing an upper portion of the stack structure in the first direction and dividing the string selection line along the second direction, wherein the lower separation structure and the first upper separation structure are vertically overlapped with one of the columns of the vertical channel structures, and the second upper separation structures are provided between the vertical channel structures. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023186990A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023186990A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023186990A13</originalsourceid><addsrcrecordid>eNqNyjsKwkAQANA0FqLeYSB1IB8QUy6zoxnYnYX9BFKFIGslGoj3x8YDWL3m7YsxDp6o0mxJAjtRBgJZRic6YXQeLFnnJ9A0MhIo0UCGMHonjBCmEMkCC5qkWW4QB4KgLB2L3WN5bvn081CUV4o4VHl9z3lbl3t-5c-cQlu3XXM5932tmu6_9QV6jDHl</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME</title><source>esp@cenet</source><creator>KANAMORI, Kohji ; HAN, Jeehoon ; KIM, Seung Yoon</creator><creatorcontrib>KANAMORI, Kohji ; HAN, Jeehoon ; KIM, Seung Yoon</creatorcontrib><description>A three-dimensional semiconductor memory device includes: a stack structure including a ground selection line, first word lines, second word lines, and a string selection line, which are sequentially stacked on a substrate; vertical channel structures penetrating the stack structure and arranged to form a plurality of columns; a lower separation structure crossing a lower portion of the stack structure in a first direction and dividing the ground selection line along a second direction intersecting the first direction; and first and second upper separation structures crossing an upper portion of the stack structure in the first direction and dividing the string selection line along the second direction, wherein the lower separation structure and the first upper separation structure are vertically overlapped with one of the columns of the vertical channel structures, and the second upper separation structures are provided between the vertical channel structures.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230615&DB=EPODOC&CC=US&NR=2023186990A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25555,76308</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230615&DB=EPODOC&CC=US&NR=2023186990A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KANAMORI, Kohji</creatorcontrib><creatorcontrib>HAN, Jeehoon</creatorcontrib><creatorcontrib>KIM, Seung Yoon</creatorcontrib><title>THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME</title><description>A three-dimensional semiconductor memory device includes: a stack structure including a ground selection line, first word lines, second word lines, and a string selection line, which are sequentially stacked on a substrate; vertical channel structures penetrating the stack structure and arranged to form a plurality of columns; a lower separation structure crossing a lower portion of the stack structure in a first direction and dividing the ground selection line along a second direction intersecting the first direction; and first and second upper separation structures crossing an upper portion of the stack structure in the first direction and dividing the string selection line along the second direction, wherein the lower separation structure and the first upper separation structure are vertically overlapped with one of the columns of the vertical channel structures, and the second upper separation structures are provided between the vertical channel structures.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjsKwkAQANA0FqLeYSB1IB8QUy6zoxnYnYX9BFKFIGslGoj3x8YDWL3m7YsxDp6o0mxJAjtRBgJZRic6YXQeLFnnJ9A0MhIo0UCGMHonjBCmEMkCC5qkWW4QB4KgLB2L3WN5bvn081CUV4o4VHl9z3lbl3t-5c-cQlu3XXM5932tmu6_9QV6jDHl</recordid><startdate>20230615</startdate><enddate>20230615</enddate><creator>KANAMORI, Kohji</creator><creator>HAN, Jeehoon</creator><creator>KIM, Seung Yoon</creator><scope>EVB</scope></search><sort><creationdate>20230615</creationdate><title>THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME</title><author>KANAMORI, Kohji ; HAN, Jeehoon ; KIM, Seung Yoon</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023186990A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>KANAMORI, Kohji</creatorcontrib><creatorcontrib>HAN, Jeehoon</creatorcontrib><creatorcontrib>KIM, Seung Yoon</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KANAMORI, Kohji</au><au>HAN, Jeehoon</au><au>KIM, Seung Yoon</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME</title><date>2023-06-15</date><risdate>2023</risdate><abstract>A three-dimensional semiconductor memory device includes: a stack structure including a ground selection line, first word lines, second word lines, and a string selection line, which are sequentially stacked on a substrate; vertical channel structures penetrating the stack structure and arranged to form a plurality of columns; a lower separation structure crossing a lower portion of the stack structure in a first direction and dividing the ground selection line along a second direction intersecting the first direction; and first and second upper separation structures crossing an upper portion of the stack structure in the first direction and dividing the string selection line along the second direction, wherein the lower separation structure and the first upper separation structure are vertically overlapped with one of the columns of the vertical channel structures, and the second upper separation structures are provided between the vertical channel structures.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
title | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME |
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