READ CLOCK START AND STOP FOR SYNCHRONOUS MEMORIES

A memory includes a read clock state machine and a read clock driver circuit. The read clock state machine has a first input for receiving a read command signal, a second input for receiving a read clock mode signal, and an output for providing a drive enable signal. The read clock driver circuit ha...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Gopalakrishnan, Karthik, Nygren, Aaron John, Liu, Tsun Ho
Format: Patent
Sprache:eng
Schlagworte:
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