OUTPUT VOLTAGE GLITCH REDUCTION IN TEST SYSTEMS

OUTPUT VOLTAGE GLITCH REDUCTION IN TEST SYSTEMS

A clamp circuit comprises an output transistor and a replica transistor coupled as a current minor pair, wherein the replica transistor is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein the output current...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Harrell, Michael E, D'Aquino, Stefano I, Turvey, Anthony Eric, Pierdomenico, Jennifer W
Format: Patent
Sprache:eng
Schlagworte:
AMPLIFIERS
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Beschreibung
Zusammenfassung:A clamp circuit comprises an output transistor and a replica transistor coupled as a current minor pair, wherein the replica transistor is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein the output current is set at a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio; and a register circuit, wherein a register value stored in the register circuit sets the clamped output current value.