MEMORY DEVICE AND OPERATION METHOD THEREOF

Disclosed is a memory device includes a memory block that is connected with a plurality of wordlines, a voltage generating circuit configured to output a first non-selection voltage through a plurality of driving lines, and an address decoding circuit configured to connect the plurality of driving l...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	KIM, Hyunggon, NAM, Sang-Wan, JUNG, Bong-Kil, HONG, Younho, HWANG, Juseong
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
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