Techniques For Synchronous Accesses To Storage Circuits

A memory interface circuit includes first and second memory controller circuits that asynchronously receive requests for memory accesses to first and second storage circuits. The memory interface circuit also includes first and second clock gate circuits that disable and then reenable first and second clock signals in response to a clock enable signal. The first and the second memory controller circuits perform the memory accesses to the first and the second storage circuits synchronously in response to the first and the second clock signals that have been reenabled by the first and the second clock gate circuits.