Multibit Memory Device and Method of Operating the Same

Memory devices and methods for operating the same are provided. Generally, the device includes an array of multibit-memory-cells, each operable to store multiple bits in separate locations of a charge-trapping layer, and control-circuitry coupled to the array. The control-circuitry is operable read 1st and 2nd bit values of each cell individually based on generated first and second sensed currents, where the first and second sensed currents correspond to charges trapped in first and second bit locations. The control-circuitry executes an algorithm based on the first and second sensed currents and determines a logic state of the cell. In one embodiment, the control-circuitry averages the sensed currents, and compares this to a reference current to determine the logic state. In another, the 2nd bit value is a complement of the 1st, and the control-circuitry compares the currents to determine the logic state without use of a reference current.