ALLOCATION OF DATA SUB-TENSORS ONTO HARDWARE SUB-ARRAYS

ALLOCATION OF DATA SUB-TENSORS ONTO HARDWARE SUB-ARRAYS

Certain aspects of the present disclosure provide techniques for improved hardware utilization. An input data tensor is divided into a first plurality of sub-tensors, and a plurality of logical sub-arrays in a physical multiply-and-accumulate (MAC) array is identified. For each respective sub-tensor...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: PALIWAL, Niraj Shantilal, PARK, Hee Jun, RYCHLIK, Bohuslav
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Certain aspects of the present disclosure provide techniques for improved hardware utilization. An input data tensor is divided into a first plurality of sub-tensors, and a plurality of logical sub-arrays in a physical multiply-and-accumulate (MAC) array is identified. For each respective sub-tensor of the first plurality of sub-tensors, the respective sub-tensor is mapped to a respective logical sub-array of the plurality of logical sub-arrays, and the respective sub-tensor is processed using the respective logical sub-array.