TECHNIQUES ASSOCIATED WITH MAPPING SYSTEM MEMORY PHYSICAL ADDRESSES TO PROXIMITY DOMAINS

Examples include techniques associated with mapping system memory physical addresses to proximity domains. Examples include mapping system memory physical addresses for a memory coupled with a multi-die system to proximity domains that include cores of a multi-core processor and the associated level...

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Hauptverfasser:	VAN DOREN, Stephen R, GUPTA, Ritu
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	VAN DOREN, Stephen R GUPTA, Ritu
description	Examples include techniques associated with mapping system memory physical addresses to proximity domains. Examples include mapping system memory physical addresses for a memory coupled with a multi-die system to proximity domains that include cores of a multi-core processor and the associated level 3 (L3) cache for use by each core included in a respective proximity domain. The mapping is to facilitate cache line ownership of a cache line in an L3 cache by an input/output device or agent located on a separate die from the multi-core processor.
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title	TECHNIQUES ASSOCIATED WITH MAPPING SYSTEM MEMORY PHYSICAL ADDRESSES TO PROXIMITY DOMAINS
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