LOGICAL CLOCK CONNECTION IN AN INTEGRATED CIRCUIT DESIGN
A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrat...
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| creator | Schubert, Klaus-Dieter Roesner, Wolfgang Williams, Derek E Cargnoni, Robert Alan El-Zein, Ali S Paruthi, Viresh McQuade, Edward Armayor Geukes, Benedikt Shuma, Stephen Gerard Ng, Alvan Wing Wood, Michael Hemsley Shum, Chung-Lung K |
| description | A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated. |
| format | Patent |
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The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. 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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | LOGICAL CLOCK CONNECTION IN AN INTEGRATED CIRCUIT DESIGN |
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