TEST STRUCTURE FOR VOID AND TOPOGRAPHY MONITORING IN A FLASH MEMORY DEVICE
A semiconductor device includes a memory region including an array of memory cell devices, and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first raised portion of a substrate, a first polysilicon structure adjacent to the firs...
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| creator | LIAO, Ken-Ying SUNG, Chih-Wei TUNG, Huai-jen LIN, Tzu-Pin CHEN, Po-Zen YANG, Yung-Lung WU, Yen-Jou |
| description | A semiconductor device includes a memory region including an array of memory cell devices, and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first raised portion of a substrate, a first polysilicon structure adjacent to the first raised portion and in a region between the first raised portion and a second raised portion of the substrate, a first spacer adjacent to the first polysilicon structure, and a second gate stack on the second raised portion, a second polysilicon structure adjacent to the second raised portion and in the region between the first raised portion and the second raised portion, and a second spacer adjacent to the second polysilicon structure. The semiconductor device includes an interlayer dielectric layer over at least a portion of the memory region and at least a portion of the test region. |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | TEST STRUCTURE FOR VOID AND TOPOGRAPHY MONITORING IN A FLASH MEMORY DEVICE |
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